2016-03-23 02:27:53 +01:00
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/*
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2016-07-05 16:05:53 +02:00
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* This file is part of Luma3DS
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2019-02-25 02:04:32 +01:00
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* Copyright (C) 2016-2019 Aurora Wright, TuxSH
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2016-03-23 02:27:53 +01:00
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*
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2016-07-05 16:05:53 +02:00
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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2017-06-05 02:02:04 +02:00
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* Additional Terms 7.b and 7.c of GPLv3 apply to this file:
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* * Requiring preservation of specified reasonable legal notices or
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* author attributions in that material or in the Appropriate Legal
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* Notices displayed by works containing it.
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* * Prohibiting misrepresentation of the origin of that material,
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* or requiring that modified versions of such material be marked in
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* reasonable ways as different from the original version.
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2016-07-05 16:05:53 +02:00
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*/
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/*
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2016-04-23 01:43:11 +02:00
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* Crypto libs from http://github.com/b1l1s/ctr
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2016-09-20 14:29:26 +02:00
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* kernel9Loader code originally adapted from https://github.com/Reisyukaku/ReiNand/blob/228c378255ba693133dec6f3368e14d386f2cde7/source/crypto.c#L233
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2016-09-18 23:50:44 +02:00
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* decryptNusFirm code adapted from https://github.com/mid-kid/CakesForeveryWan/blob/master/source/firm.c
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2016-10-11 16:52:51 +02:00
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* ctrNandWrite logic adapted from https://github.com/d0k3/GodMode9/blob/master/source/nand/nand.c
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2016-03-23 02:27:53 +01:00
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*/
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2015-08-21 20:11:23 +02:00
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#include "crypto.h"
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#include "memory.h"
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2017-06-10 02:39:00 +02:00
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#include "emunand.h"
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2016-10-10 01:34:53 +02:00
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#include "utils.h"
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2019-03-13 13:53:29 +01:00
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#include "alignedseqmemcpy.h"
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2015-08-21 20:11:23 +02:00
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#include "fatfs/sdmmc/sdmmc.h"
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/****************************************************************
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2016-07-05 16:05:53 +02:00
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* Crypto libs
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2015-08-21 20:11:23 +02:00
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****************************************************************/
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/* original version by megazig */
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#ifndef __thumb__
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#define BSWAP32(x) {\
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2016-06-12 22:14:52 +02:00
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__asm__\
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(\
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"eor r1, %1, %1, ror #16\n\t"\
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"bic r1, r1, #0xFF0000\n\t"\
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"mov %0, %1, ror #8\n\t"\
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"eor %0, %0, r1, lsr #8\n\t"\
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:"=r"(x)\
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:"0"(x)\
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:"r1"\
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);\
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2015-08-21 20:11:23 +02:00
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};
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#define ADD_u128_u32(u128_0, u128_1, u128_2, u128_3, u32_0) {\
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__asm__\
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2016-06-12 22:14:52 +02:00
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(\
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"adds %0, %4\n\t"\
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"addcss %1, %1, #1\n\t"\
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"addcss %2, %2, #1\n\t"\
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"addcs %3, %3, #1\n\t"\
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: "+r"(u128_0), "+r"(u128_1), "+r"(u128_2), "+r"(u128_3)\
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: "r"(u32_0)\
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: "cc"\
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);\
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2015-08-21 20:11:23 +02:00
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}
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#else
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#define BSWAP32(x) {x = __builtin_bswap32(x);}
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#define ADD_u128_u32(u128_0, u128_1, u128_2, u128_3, u32_0) {\
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__asm__\
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2016-06-12 22:14:52 +02:00
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(\
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"mov r4, #0\n\t"\
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"add %0, %0, %4\n\t"\
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"adc %1, %1, r4\n\t"\
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"adc %2, %2, r4\n\t"\
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"adc %3, %3, r4\n\t"\
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: "+r"(u128_0), "+r"(u128_1), "+r"(u128_2), "+r"(u128_3)\
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: "r"(u32_0)\
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: "cc", "r4"\
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);\
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2015-08-21 20:11:23 +02:00
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}
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#endif /*__thumb__*/
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2016-03-13 16:48:57 +01:00
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static void aes_setkey(u8 keyslot, const void *key, u32 keyType, u32 mode)
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2015-08-21 20:11:23 +02:00
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{
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2016-06-12 22:14:52 +02:00
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u32 *key32 = (u32 *)key;
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*REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode;
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2017-02-09 20:35:39 +01:00
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if(keyslot <= 3)
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{
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2017-05-29 14:23:45 +02:00
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if((mode & AES_CNT_INPUT_ORDER) == AES_INPUT_TWLREVERSED)
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2017-02-09 20:35:39 +01:00
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{
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REGs_AESTWLKEYS[keyslot][keyType][0] = key32[3];
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REGs_AESTWLKEYS[keyslot][keyType][1] = key32[2];
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REGs_AESTWLKEYS[keyslot][keyType][2] = key32[1];
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REGs_AESTWLKEYS[keyslot][keyType][3] = key32[0];
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}
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else
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{
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REGs_AESTWLKEYS[keyslot][keyType][0] = key32[0];
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REGs_AESTWLKEYS[keyslot][keyType][1] = key32[1];
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REGs_AESTWLKEYS[keyslot][keyType][2] = key32[2];
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REGs_AESTWLKEYS[keyslot][keyType][3] = key32[3];
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}
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}
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else if(keyslot < 0x40)
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{
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*REG_AESKEYCNT = (*REG_AESKEYCNT >> 6 << 6) | keyslot | AES_KEYCNT_WRITE;
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REG_AESKEYFIFO[keyType] = key32[0];
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REG_AESKEYFIFO[keyType] = key32[1];
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REG_AESKEYFIFO[keyType] = key32[2];
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REG_AESKEYFIFO[keyType] = key32[3];
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}
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2015-08-21 20:11:23 +02:00
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}
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2016-03-10 14:58:11 +01:00
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static void aes_use_keyslot(u8 keyslot)
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2015-08-21 20:11:23 +02:00
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{
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2016-06-12 22:14:52 +02:00
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if(keyslot > 0x3F)
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return;
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2015-08-21 20:11:23 +02:00
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2016-06-12 22:14:52 +02:00
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*REG_AESKEYSEL = keyslot;
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*REG_AESCNT = *REG_AESCNT | 0x04000000; /* mystery bit */
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2015-08-21 20:11:23 +02:00
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}
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2016-03-13 16:48:57 +01:00
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static void aes_setiv(const void *iv, u32 mode)
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2015-08-21 20:11:23 +02:00
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{
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2016-06-12 22:14:52 +02:00
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const u32 *iv32 = (const u32 *)iv;
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*REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode;
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2016-10-07 14:27:30 +02:00
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//Word order for IV can't be changed in REG_AESCNT and always default to reversed
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2016-06-12 22:14:52 +02:00
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if(mode & AES_INPUT_NORMAL)
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{
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REG_AESCTR[0] = iv32[3];
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REG_AESCTR[1] = iv32[2];
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REG_AESCTR[2] = iv32[1];
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REG_AESCTR[3] = iv32[0];
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}
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else
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{
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REG_AESCTR[0] = iv32[0];
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REG_AESCTR[1] = iv32[1];
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REG_AESCTR[2] = iv32[2];
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REG_AESCTR[3] = iv32[3];
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}
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2015-08-21 20:11:23 +02:00
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}
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2016-03-10 14:58:11 +01:00
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static void aes_advctr(void *ctr, u32 val, u32 mode)
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2015-08-21 20:11:23 +02:00
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{
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2016-06-12 22:14:52 +02:00
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u32 *ctr32 = (u32 *)ctr;
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2016-09-22 15:09:52 +02:00
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2016-06-12 22:14:52 +02:00
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int i;
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if(mode & AES_INPUT_BE)
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{
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2016-10-07 14:27:30 +02:00
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for(i = 0; i < 4; ++i) //Endian swap
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2016-06-12 22:14:52 +02:00
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BSWAP32(ctr32[i]);
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}
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2016-09-22 15:09:52 +02:00
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2016-06-12 22:14:52 +02:00
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if(mode & AES_INPUT_NORMAL)
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{
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ADD_u128_u32(ctr32[3], ctr32[2], ctr32[1], ctr32[0], val);
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}
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else
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{
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ADD_u128_u32(ctr32[0], ctr32[1], ctr32[2], ctr32[3], val);
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}
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2016-09-22 15:09:52 +02:00
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2016-06-12 22:14:52 +02:00
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if(mode & AES_INPUT_BE)
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{
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2016-10-07 14:27:30 +02:00
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for(i = 0; i < 4; ++i) //Endian swap
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2016-06-12 22:14:52 +02:00
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BSWAP32(ctr32[i]);
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}
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2015-08-21 20:11:23 +02:00
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}
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2016-03-10 14:58:11 +01:00
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static void aes_change_ctrmode(void *ctr, u32 fromMode, u32 toMode)
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2015-08-21 20:11:23 +02:00
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{
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2016-06-12 22:14:52 +02:00
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u32 *ctr32 = (u32 *)ctr;
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int i;
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if((fromMode ^ toMode) & AES_CNT_INPUT_ENDIAN)
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{
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for(i = 0; i < 4; ++i)
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BSWAP32(ctr32[i]);
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}
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if((fromMode ^ toMode) & AES_CNT_INPUT_ORDER)
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{
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u32 temp = ctr32[0];
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ctr32[0] = ctr32[3];
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ctr32[3] = temp;
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temp = ctr32[1];
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ctr32[1] = ctr32[2];
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ctr32[2] = temp;
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}
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2015-08-21 20:11:23 +02:00
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}
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2016-03-10 14:58:11 +01:00
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static void aes_batch(void *dst, const void *src, u32 blockCount)
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2015-08-21 20:11:23 +02:00
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{
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2016-06-12 22:14:52 +02:00
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*REG_AESBLKCNT = blockCount << 16;
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*REG_AESCNT |= AES_CNT_START;
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2016-09-22 15:09:52 +02:00
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2016-06-12 22:14:52 +02:00
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const u32 *src32 = (const u32 *)src;
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u32 *dst32 = (u32 *)dst;
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2016-09-22 15:09:52 +02:00
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2016-06-12 22:14:52 +02:00
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u32 wbc = blockCount;
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u32 rbc = blockCount;
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2016-09-22 15:09:52 +02:00
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2016-06-12 22:14:52 +02:00
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while(rbc)
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{
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2016-10-07 14:27:30 +02:00
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if(wbc && ((*REG_AESCNT & 0x1F) <= 0xC)) //There's space for at least 4 ints
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2016-06-12 22:14:52 +02:00
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{
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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wbc--;
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}
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2016-09-22 15:09:52 +02:00
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2016-10-07 14:27:30 +02:00
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if(rbc && ((*REG_AESCNT & (0x1F << 0x5)) >= (0x4 << 0x5))) //At least 4 ints available for read
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2016-06-12 22:14:52 +02:00
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{
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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rbc--;
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}
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}
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2015-08-21 20:11:23 +02:00
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}
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2017-05-26 03:15:22 +02:00
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static void aes(void *dst, const void *src, u32 blockCount, void *iv, u32 mode, u32 ivMode)
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2015-08-21 20:11:23 +02:00
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{
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2016-06-12 22:14:52 +02:00
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*REG_AESCNT = mode |
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AES_CNT_INPUT_ORDER | AES_CNT_OUTPUT_ORDER |
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AES_CNT_INPUT_ENDIAN | AES_CNT_OUTPUT_ENDIAN |
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AES_CNT_FLUSH_READ | AES_CNT_FLUSH_WRITE;
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u32 blocks;
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while(blockCount != 0)
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{
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if((mode & AES_ALL_MODES) != AES_ECB_ENCRYPT_MODE
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&& (mode & AES_ALL_MODES) != AES_ECB_DECRYPT_MODE)
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aes_setiv(iv, ivMode);
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blocks = (blockCount >= 0xFFFF) ? 0xFFFF : blockCount;
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2016-10-07 14:27:30 +02:00
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//Save the last block for the next decryption CBC batch's iv
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2016-06-12 22:14:52 +02:00
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if((mode & AES_ALL_MODES) == AES_CBC_DECRYPT_MODE)
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{
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memcpy(iv, src + (blocks - 1) * AES_BLOCK_SIZE, AES_BLOCK_SIZE);
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aes_change_ctrmode(iv, AES_INPUT_BE | AES_INPUT_NORMAL, ivMode);
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}
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2016-10-07 14:27:30 +02:00
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//Process the current batch
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2016-06-12 22:14:52 +02:00
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aes_batch(dst, src, blocks);
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2016-10-07 14:27:30 +02:00
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//Save the last block for the next encryption CBC batch's iv
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2016-06-12 22:14:52 +02:00
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if((mode & AES_ALL_MODES) == AES_CBC_ENCRYPT_MODE)
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{
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memcpy(iv, dst + (blocks - 1) * AES_BLOCK_SIZE, AES_BLOCK_SIZE);
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aes_change_ctrmode(iv, AES_INPUT_BE | AES_INPUT_NORMAL, ivMode);
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}
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2016-09-22 15:09:52 +02:00
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2016-10-07 14:27:30 +02:00
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//Advance counter for CTR mode
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2016-06-12 22:14:52 +02:00
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else if((mode & AES_ALL_MODES) == AES_CTR_MODE)
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aes_advctr(iv, blocks, ivMode);
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src += blocks * AES_BLOCK_SIZE;
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dst += blocks * AES_BLOCK_SIZE;
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blockCount -= blocks;
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}
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2015-08-21 20:11:23 +02:00
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}
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2016-04-11 05:15:44 +02:00
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static void sha_wait_idle()
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{
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2016-06-12 22:14:52 +02:00
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while(*REG_SHA_CNT & 1);
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2016-04-11 05:15:44 +02:00
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}
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2017-05-18 01:05:56 +02:00
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void sha(void *res, const void *src, u32 size, u32 mode)
|
2016-04-11 05:15:44 +02:00
|
|
|
{
|
2016-06-12 22:14:52 +02:00
|
|
|
sha_wait_idle();
|
|
|
|
*REG_SHA_CNT = mode | SHA_CNT_OUTPUT_ENDIAN | SHA_NORMAL_ROUND;
|
2016-09-22 15:09:52 +02:00
|
|
|
|
2019-03-13 13:53:29 +01:00
|
|
|
const u8 *src8 = (const u8 *)src;
|
2016-06-12 22:14:52 +02:00
|
|
|
while(size >= 0x40)
|
|
|
|
{
|
|
|
|
sha_wait_idle();
|
2019-03-13 13:53:29 +01:00
|
|
|
alignedseqmemcpy((void *)REG_SHA_INFIFO, src8, 0x40);
|
2016-06-12 22:14:52 +02:00
|
|
|
|
2019-03-13 13:53:29 +01:00
|
|
|
src8 += 0x40;
|
2016-06-12 22:14:52 +02:00
|
|
|
size -= 0x40;
|
|
|
|
}
|
2016-09-22 15:09:52 +02:00
|
|
|
|
2016-06-12 22:14:52 +02:00
|
|
|
sha_wait_idle();
|
2019-03-13 13:53:29 +01:00
|
|
|
alignedseqmemcpy((void *)REG_SHA_INFIFO, src8, size);
|
2016-09-22 15:09:52 +02:00
|
|
|
|
2016-06-12 22:14:52 +02:00
|
|
|
*REG_SHA_CNT = (*REG_SHA_CNT & ~SHA_NORMAL_ROUND) | SHA_FINAL_ROUND;
|
2016-09-22 15:09:52 +02:00
|
|
|
|
2016-06-12 22:14:52 +02:00
|
|
|
while(*REG_SHA_CNT & SHA_FINAL_ROUND);
|
|
|
|
sha_wait_idle();
|
2016-09-22 14:48:28 +02:00
|
|
|
|
2016-06-12 22:14:52 +02:00
|
|
|
u32 hashSize = SHA_256_HASH_SIZE;
|
|
|
|
if(mode == SHA_224_MODE)
|
|
|
|
hashSize = SHA_224_HASH_SIZE;
|
|
|
|
else if(mode == SHA_1_MODE)
|
|
|
|
hashSize = SHA_1_HASH_SIZE;
|
|
|
|
|
2019-03-15 16:17:57 +01:00
|
|
|
alignedseqmemcpy(res, (void *)REG_SHA_HASH, hashSize);
|
2016-04-11 05:15:44 +02:00
|
|
|
}
|
|
|
|
|
2016-09-19 00:14:32 +02:00
|
|
|
/*****************************************************************/
|
2016-02-08 03:37:03 +01:00
|
|
|
|
2016-11-14 00:08:41 +01:00
|
|
|
__attribute__((aligned(4))) static u8 nandCtr[AES_BLOCK_SIZE];
|
2016-08-03 14:13:26 +02:00
|
|
|
static u8 nandSlot;
|
2017-05-26 03:07:39 +02:00
|
|
|
static u32 fatStart = 0;
|
2016-04-11 05:15:44 +02:00
|
|
|
|
2017-09-22 18:05:03 +02:00
|
|
|
FirmwareSource firmSource = FIRMWARE_SYSNAND;
|
2016-10-10 01:34:53 +02:00
|
|
|
|
2017-05-24 15:18:31 +02:00
|
|
|
__attribute__((aligned(4))) static const u8 key1s[2][AES_BLOCK_SIZE] = {
|
|
|
|
{0x07, 0x29, 0x44, 0x38, 0xF8, 0xC9, 0x75, 0x93, 0xAA, 0x0E, 0x4A, 0xB4, 0xAE, 0x84, 0xC1, 0xD8},
|
|
|
|
{0xA2, 0xF4, 0x00, 0x3C, 0x7A, 0x95, 0x10, 0x25, 0xDF, 0x4E, 0x9E, 0x74, 0xE3, 0x0C, 0x92, 0x99}
|
|
|
|
},
|
|
|
|
key2s[2][AES_BLOCK_SIZE] = {
|
|
|
|
{0x42, 0x3F, 0x81, 0x7A, 0x23, 0x52, 0x58, 0x31, 0x6E, 0x75, 0x8E, 0x3A, 0x39, 0x43, 0x2E, 0xD0},
|
|
|
|
{0xFF, 0x77, 0xA0, 0x9A, 0x99, 0x81, 0xE9, 0x48, 0xEC, 0x51, 0xC9, 0x32, 0x5D, 0x14, 0xEC, 0x25}
|
|
|
|
};
|
|
|
|
|
2017-05-26 03:07:39 +02:00
|
|
|
int ctrNandInit(void)
|
2016-04-11 05:15:44 +02:00
|
|
|
{
|
2016-11-11 18:31:38 +01:00
|
|
|
__attribute__((aligned(4))) u8 cid[AES_BLOCK_SIZE],
|
|
|
|
shaSum[SHA_256_HASH_SIZE];
|
2016-04-11 05:15:44 +02:00
|
|
|
|
2016-04-14 17:10:55 +02:00
|
|
|
sdmmc_get_cid(1, (u32 *)cid);
|
2016-09-19 14:57:36 +02:00
|
|
|
sha(shaSum, cid, sizeof(cid), SHA_256_MODE);
|
|
|
|
memcpy(nandCtr, shaSum, sizeof(nandCtr));
|
2016-03-06 16:24:42 +01:00
|
|
|
|
2017-05-26 03:07:39 +02:00
|
|
|
nandSlot = ISN3DS ? 0x05 : 0x04;
|
|
|
|
|
|
|
|
int result;
|
2017-05-26 03:15:22 +02:00
|
|
|
u8 __attribute__((aligned(4))) temp[0x200];
|
2017-05-26 03:07:39 +02:00
|
|
|
|
|
|
|
//Read NCSD header
|
|
|
|
result = firmSource == FIRMWARE_SYSNAND ? sdmmc_nand_readsectors(0, 1, temp) : sdmmc_sdcard_readsectors(emuHeader, 1, temp);
|
|
|
|
|
|
|
|
if(!result)
|
2016-04-11 05:15:44 +02:00
|
|
|
{
|
2017-05-26 03:07:39 +02:00
|
|
|
u32 partitionNum = 1; //TWL partitions need to be first
|
|
|
|
for(u8 *partitionId = temp + 0x111; *partitionId != 1; partitionId++, partitionNum++);
|
|
|
|
|
|
|
|
u32 ctrMbrOffset = *((u32 *)(temp + 0x120) + (2 * partitionNum));
|
|
|
|
|
|
|
|
//Read CTR MBR
|
|
|
|
result = ctrNandRead(ctrMbrOffset, 1, temp);
|
|
|
|
|
|
|
|
//Calculate final CTRNAND FAT offset
|
|
|
|
if(!result) fatStart = ctrMbrOffset + *(u32 *)(temp + 0x1C6);
|
2016-04-11 05:15:44 +02:00
|
|
|
}
|
2017-05-26 03:07:39 +02:00
|
|
|
|
|
|
|
return result;
|
2016-04-11 05:15:44 +02:00
|
|
|
}
|
|
|
|
|
2016-10-07 14:27:30 +02:00
|
|
|
int ctrNandRead(u32 sector, u32 sectorCount, u8 *outbuf)
|
2016-04-02 17:58:06 +02:00
|
|
|
{
|
2016-11-11 18:31:38 +01:00
|
|
|
__attribute__((aligned(4))) u8 tmpCtr[sizeof(nandCtr)];
|
2016-09-19 14:57:36 +02:00
|
|
|
memcpy(tmpCtr, nandCtr, sizeof(nandCtr));
|
|
|
|
aes_advctr(tmpCtr, ((sector + fatStart) * 0x200) / AES_BLOCK_SIZE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2016-04-11 05:15:44 +02:00
|
|
|
|
|
|
|
//Read
|
2016-10-07 14:27:30 +02:00
|
|
|
int result;
|
2016-06-12 22:14:52 +02:00
|
|
|
if(firmSource == FIRMWARE_SYSNAND)
|
2016-04-11 05:15:44 +02:00
|
|
|
result = sdmmc_nand_readsectors(sector + fatStart, sectorCount, outbuf);
|
|
|
|
else
|
|
|
|
{
|
|
|
|
sector += emuOffset;
|
|
|
|
result = sdmmc_sdcard_readsectors(sector + fatStart, sectorCount, outbuf);
|
|
|
|
}
|
|
|
|
|
|
|
|
//Decrypt
|
|
|
|
aes_use_keyslot(nandSlot);
|
2016-09-19 14:57:36 +02:00
|
|
|
aes(outbuf, outbuf, sectorCount * 0x200 / AES_BLOCK_SIZE, tmpCtr, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2016-04-11 05:15:44 +02:00
|
|
|
|
|
|
|
return result;
|
2016-02-08 03:37:03 +01:00
|
|
|
}
|
|
|
|
|
2016-10-11 16:52:51 +02:00
|
|
|
int ctrNandWrite(u32 sector, u32 sectorCount, const u8 *inbuf)
|
2016-10-08 01:46:41 +02:00
|
|
|
{
|
2017-05-24 19:52:09 +02:00
|
|
|
u8 *buffer = (u8 *)0xFFF00000;
|
|
|
|
u32 bufferSize = 0x4000;
|
2016-10-11 16:52:51 +02:00
|
|
|
|
2016-11-11 18:31:38 +01:00
|
|
|
__attribute__((aligned(4))) u8 tmpCtr[sizeof(nandCtr)];
|
2016-10-08 01:46:41 +02:00
|
|
|
memcpy(tmpCtr, nandCtr, sizeof(nandCtr));
|
|
|
|
aes_advctr(tmpCtr, ((sector + fatStart) * 0x200) / AES_BLOCK_SIZE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_use_keyslot(nandSlot);
|
|
|
|
|
2016-10-11 16:52:51 +02:00
|
|
|
int result = 0;
|
2016-10-11 16:59:55 +02:00
|
|
|
for(u32 tempSector = 0; tempSector < sectorCount && !result; tempSector += bufferSize / 0x200)
|
2016-10-11 16:52:51 +02:00
|
|
|
{
|
2016-10-11 16:59:55 +02:00
|
|
|
u32 tempCount = (bufferSize / 0x200) < (sectorCount - tempSector) ? (bufferSize / 0x200) : (sectorCount - tempSector);
|
2016-10-11 16:52:51 +02:00
|
|
|
|
2016-10-11 16:59:55 +02:00
|
|
|
memcpy(buffer, inbuf + (tempSector * 0x200), tempCount * 0x200);
|
2016-10-11 16:52:51 +02:00
|
|
|
|
|
|
|
//Encrypt
|
2016-10-11 16:59:55 +02:00
|
|
|
aes(buffer, buffer, tempCount * 0x200 / AES_BLOCK_SIZE, tmpCtr, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2016-10-11 16:52:51 +02:00
|
|
|
|
|
|
|
//Write
|
2016-10-11 16:59:55 +02:00
|
|
|
result = sdmmc_nand_writesectors(tempSector + sector + fatStart, tempCount, buffer);
|
2016-10-11 16:52:51 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return result;
|
2016-10-08 01:46:41 +02:00
|
|
|
}
|
|
|
|
|
2017-06-10 02:39:00 +02:00
|
|
|
u32 decryptExeFs(Cxi *cxi)
|
2016-04-11 05:15:44 +02:00
|
|
|
{
|
2017-06-10 02:39:00 +02:00
|
|
|
if(memcmp(cxi->ncch.magic, "NCCH", 4) != 0) return 0;
|
|
|
|
|
|
|
|
if(cxi->ncch.exeFsOffset != 5) return 0;
|
|
|
|
|
|
|
|
u8 *exeFsOffset = (u8 *)cxi + 6 * 0x200;
|
2016-11-15 19:29:48 +01:00
|
|
|
u32 exeFsSize = (cxi->ncch.exeFsSize - 1) * 0x200;
|
2017-06-10 02:39:00 +02:00
|
|
|
|
|
|
|
if(exeFsSize > 0x400000) return 0;
|
|
|
|
|
2016-11-15 19:29:48 +01:00
|
|
|
__attribute__((aligned(4))) u8 ncchCtr[AES_BLOCK_SIZE] = {0};
|
2016-10-10 01:34:53 +02:00
|
|
|
|
2016-11-15 19:29:48 +01:00
|
|
|
for(u32 i = 0; i < 8; i++)
|
|
|
|
ncchCtr[7 - i] = cxi->ncch.partitionId[i];
|
|
|
|
ncchCtr[8] = 2;
|
2016-10-10 01:34:53 +02:00
|
|
|
|
2016-11-15 19:29:48 +01:00
|
|
|
aes_setkey(0x2C, cxi, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_advctr(ncchCtr, 0x200 / AES_BLOCK_SIZE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_use_keyslot(0x2C);
|
|
|
|
aes(cxi, exeFsOffset, exeFsSize / AES_BLOCK_SIZE, ncchCtr, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2016-10-10 01:34:53 +02:00
|
|
|
|
2017-06-10 02:39:00 +02:00
|
|
|
return memcmp(cxi, "FIRM", 4) == 0 ? exeFsSize : 0;
|
2016-02-08 03:37:03 +01:00
|
|
|
}
|
2015-08-21 20:11:23 +02:00
|
|
|
|
2017-06-10 02:39:00 +02:00
|
|
|
u32 decryptNusFirm(const Ticket *ticket, Cxi *cxi, u32 ncchSize)
|
2016-09-18 23:50:44 +02:00
|
|
|
{
|
2017-06-10 02:39:00 +02:00
|
|
|
if(memcmp(ticket->sigIssuer, "Root", 4) != 0) return 0;
|
2016-10-10 01:34:53 +02:00
|
|
|
|
2017-06-09 14:26:51 +02:00
|
|
|
__attribute__((aligned(4))) static const u8 keyY0x3D[AES_BLOCK_SIZE] = {0x0C, 0x76, 0x72, 0x30, 0xF0, 0x99, 0x8F, 0x1C, 0x46, 0x82, 0x82, 0x02, 0xFA, 0xAC, 0xBE, 0x4C};
|
2016-11-15 19:29:48 +01:00
|
|
|
__attribute__((aligned(4))) u8 titleKey[AES_BLOCK_SIZE],
|
2016-11-15 20:18:28 +01:00
|
|
|
cetkIv[AES_BLOCK_SIZE] = {0};
|
2016-11-15 19:29:48 +01:00
|
|
|
memcpy(titleKey, ticket->titleKey, sizeof(titleKey));
|
|
|
|
memcpy(cetkIv, ticket->titleId, sizeof(ticket->titleId));
|
2016-09-18 23:50:44 +02:00
|
|
|
|
2016-11-15 19:29:48 +01:00
|
|
|
aes_setkey(0x3D, keyY0x3D, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_use_keyslot(0x3D);
|
|
|
|
aes(titleKey, titleKey, 1, cetkIv, AES_CBC_DECRYPT_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2016-09-18 23:50:44 +02:00
|
|
|
|
2016-11-15 19:29:48 +01:00
|
|
|
__attribute__((aligned(4))) u8 ncchIv[AES_BLOCK_SIZE] = {0};
|
2016-09-18 23:50:44 +02:00
|
|
|
|
2016-11-15 19:29:48 +01:00
|
|
|
aes_setkey(0x16, titleKey, AES_KEYNORMAL, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_use_keyslot(0x16);
|
|
|
|
aes(cxi, cxi, ncchSize / AES_BLOCK_SIZE, ncchIv, AES_CBC_DECRYPT_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2016-10-10 01:34:53 +02:00
|
|
|
|
2016-11-15 19:29:48 +01:00
|
|
|
return decryptExeFs(cxi);
|
2016-09-18 23:50:44 +02:00
|
|
|
}
|
|
|
|
|
2017-05-24 15:18:31 +02:00
|
|
|
static inline void twlConsoleInfoInit(void)
|
|
|
|
{
|
2017-05-29 14:23:45 +02:00
|
|
|
u64 twlConsoleId = ISDEVUNIT ? OTP_DEVCONSOLEID : (0x80000000ULL | (*(vu64 *)0x01FFB808 ^ 0x8C267B7B358A6AFULL));
|
2017-05-24 15:18:31 +02:00
|
|
|
CFG_TWLUNITINFO = CFG_UNITINFO;
|
|
|
|
OTP_TWLCONSOLEID = twlConsoleId;
|
|
|
|
|
|
|
|
*REG_AESCNT = 0;
|
|
|
|
|
2017-05-29 15:46:37 +02:00
|
|
|
vu32 *k3X = REGs_AESTWLKEYS[3][1],
|
|
|
|
*k1X = REGs_AESTWLKEYS[1][1];
|
2017-05-24 15:18:31 +02:00
|
|
|
|
|
|
|
k3X[0] = (u32)twlConsoleId;
|
|
|
|
k3X[3] = (u32)(twlConsoleId >> 32);
|
|
|
|
|
|
|
|
k1X[2] = (u32)(twlConsoleId >> 32);
|
|
|
|
k1X[3] = (u32)twlConsoleId;
|
2017-05-29 14:23:45 +02:00
|
|
|
|
|
|
|
aes_setkey(2, (u8 *)0x01FFD398, AES_KEYX, AES_INPUT_TWLNORMAL);
|
|
|
|
if(CFG_TWLUNITINFO != 0)
|
|
|
|
{
|
2017-06-09 17:29:26 +02:00
|
|
|
__attribute__((aligned(4))) static const u8 key2YDev[AES_BLOCK_SIZE] = {0x3B, 0x06, 0x86, 0x57, 0x33, 0x04, 0x88, 0x11, 0x49, 0x04, 0x6B, 0x33, 0x12, 0x02, 0xAC, 0xF3},
|
|
|
|
key3YDev[AES_BLOCK_SIZE] = {0xAA, 0xBF, 0x76, 0xF1, 0x7A, 0xB8, 0xE8, 0x66, 0x97, 0x64, 0x6A, 0x26, 0x05, 0x00, 0xA0, 0xE1};
|
2017-05-29 14:23:45 +02:00
|
|
|
|
|
|
|
k3X[1] = 0xEE7A4B1E;
|
|
|
|
k3X[2] = 0xAF42C08B;
|
|
|
|
aes_setkey(2, key2YDev, AES_KEYY, AES_INPUT_TWLNORMAL);
|
|
|
|
aes_setkey(3, key3YDev, AES_KEYY, AES_INPUT_TWLNORMAL);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
u32 last3YWord = 0xE1A00005;
|
|
|
|
__attribute__((aligned(4))) u8 key3YRetail[AES_BLOCK_SIZE];
|
|
|
|
|
|
|
|
memcpy(key3YRetail, (u8 *)0x01FFD3C8, 12);
|
|
|
|
memcpy(key3YRetail + 12, &last3YWord, 4);
|
|
|
|
|
2017-05-29 15:46:37 +02:00
|
|
|
k3X[1] = *(vu32 *)0x01FFD3A8; //"NINT"
|
|
|
|
k3X[2] = *(vu32 *)0x01FFD3AC; //"ENDO"
|
2017-05-29 14:23:45 +02:00
|
|
|
aes_setkey(2, (u8 *)0x01FFD220, AES_KEYY, AES_INPUT_TWLNORMAL);
|
|
|
|
aes_setkey(3, key3YRetail, AES_KEYY, AES_INPUT_TWLNORMAL);
|
|
|
|
}
|
2017-05-24 15:18:31 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
void setupKeyslots(void)
|
|
|
|
{
|
|
|
|
//Setup 0x24 KeyY
|
2017-06-09 14:26:51 +02:00
|
|
|
__attribute__((aligned(4))) static const u8 keyY0x24[AES_BLOCK_SIZE] = {0x74, 0xCA, 0x07, 0x48, 0x84, 0xF4, 0x22, 0x8D, 0xEB, 0x2A, 0x1C, 0xA7, 0x2D, 0x28, 0x77, 0x62};
|
2017-05-24 15:18:31 +02:00
|
|
|
aes_setkey(0x24, keyY0x24, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
|
|
|
|
//Setup 0x25 KeyX and 0x2F KeyY
|
2017-06-09 14:26:51 +02:00
|
|
|
__attribute__((aligned(4))) static const u8 keyX0x25s[2][AES_BLOCK_SIZE] = {
|
2017-05-24 15:18:31 +02:00
|
|
|
{0xCE, 0xE7, 0xD8, 0xAB, 0x30, 0xC0, 0x0D, 0xAE, 0x85, 0x0E, 0xF5, 0xE3, 0x82, 0xAC, 0x5A, 0xF3},
|
|
|
|
{0x81, 0x90, 0x7A, 0x4B, 0x6F, 0x1B, 0x47, 0x32, 0x3A, 0x67, 0x79, 0x74, 0xCE, 0x4A, 0xD7, 0x1B}
|
|
|
|
},
|
2017-06-09 17:29:26 +02:00
|
|
|
keyY0x2Fs[2][AES_BLOCK_SIZE] = {
|
2017-05-24 15:18:31 +02:00
|
|
|
{0xC3, 0x69, 0xBA, 0xA2, 0x1E, 0x18, 0x8A, 0x88, 0xA9, 0xAA, 0x94, 0xE5, 0x50, 0x6A, 0x9F, 0x16},
|
|
|
|
{0x73, 0x25, 0xC4, 0xEB, 0x14, 0x3A, 0x0D, 0x5F, 0x5D, 0xB6, 0xE5, 0xC5, 0x7A, 0x21, 0x95, 0xAC}
|
|
|
|
};
|
|
|
|
|
|
|
|
aes_setkey(0x25, keyX0x25s[ISDEVUNIT ? 1 : 0], AES_KEYX, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_setkey(0x2F, keyY0x2Fs[ISDEVUNIT ? 1 : 0], AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
|
2018-06-14 18:13:57 +02:00
|
|
|
if(ISN3DS)
|
2017-05-24 15:18:31 +02:00
|
|
|
{
|
|
|
|
//Setup 0x05 KeyY
|
2017-06-09 14:26:51 +02:00
|
|
|
__attribute__((aligned(4))) static const u8 keyY0x5[AES_BLOCK_SIZE] = {0x4D, 0x80, 0x4F, 0x4E, 0x99, 0x90, 0x19, 0x46, 0x13, 0xA2, 0x04, 0xAC, 0x58, 0x44, 0x60, 0xBE};
|
2017-05-24 15:18:31 +02:00
|
|
|
aes_setkey(0x05, keyY0x5, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
}
|
|
|
|
|
2017-05-29 14:23:45 +02:00
|
|
|
//Setup TWL keys
|
|
|
|
twlConsoleInfoInit();
|
|
|
|
|
2017-05-24 15:18:31 +02:00
|
|
|
__attribute__((aligned(4))) u8 keyBlocks[2][AES_BLOCK_SIZE] = {
|
|
|
|
{0xA4, 0x8D, 0xE4, 0xF1, 0x0B, 0x36, 0x44, 0xAA, 0x90, 0x31, 0x28, 0xFF, 0x4D, 0xCA, 0x76, 0xDF},
|
|
|
|
{0xDD, 0xDA, 0xA4, 0xC6, 0x2C, 0xC4, 0x50, 0xE9, 0xDA, 0xB6, 0x9B, 0x0D, 0x9D, 0x2A, 0x21, 0x98}
|
|
|
|
}, decKey[AES_BLOCK_SIZE];
|
|
|
|
|
2018-06-14 18:13:57 +02:00
|
|
|
//Initialize Key 0x18
|
2017-05-24 15:18:31 +02:00
|
|
|
aes_setkey(0x11, key1s[ISDEVUNIT ? 1 : 0], AES_KEYNORMAL, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_use_keyslot(0x11);
|
|
|
|
aes(decKey, keyBlocks[0], 1, NULL, AES_ECB_DECRYPT_MODE, 0);
|
|
|
|
aes_setkey(0x18, decKey, AES_KEYX, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
|
|
|
|
//Initialize Key 0x19-0x1F
|
|
|
|
aes_setkey(0x11, key2s[ISDEVUNIT ? 1 : 0], AES_KEYNORMAL, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
aes_use_keyslot(0x11);
|
|
|
|
for(u8 slot = 0x19; slot < 0x20; slot++, keyBlocks[1][0xF]++)
|
|
|
|
{
|
|
|
|
aes(decKey, keyBlocks[1], 1, NULL, AES_ECB_DECRYPT_MODE, 0);
|
|
|
|
aes_setkey(slot, decKey, AES_KEYX, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-10-08 14:23:08 +02:00
|
|
|
void kernel9Loader(Arm9Bin *arm9Section)
|
2016-04-02 17:58:06 +02:00
|
|
|
{
|
2016-09-20 14:29:26 +02:00
|
|
|
//Determine the kernel9loader version
|
|
|
|
u32 k9lVersion;
|
2017-05-20 02:08:25 +02:00
|
|
|
switch(arm9Section->magic[3])
|
2016-09-19 16:00:51 +02:00
|
|
|
{
|
2017-05-20 02:08:25 +02:00
|
|
|
case 0xFF:
|
|
|
|
k9lVersion = 0;
|
|
|
|
break;
|
|
|
|
case '1':
|
|
|
|
k9lVersion = 1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
k9lVersion = 2;
|
2016-09-19 16:00:51 +02:00
|
|
|
}
|
|
|
|
|
2016-10-10 01:34:53 +02:00
|
|
|
u32 *startOfArm9Bin = (u32 *)((u8 *)arm9Section + 0x800);
|
2017-05-20 02:08:25 +02:00
|
|
|
if(*startOfArm9Bin == 0x47704770 || *startOfArm9Bin == 0xB0862000) return; //Already decrypted
|
2016-09-19 16:00:51 +02:00
|
|
|
|
2017-02-08 12:34:07 +01:00
|
|
|
aes_setkey(0x11, k9lVersion == 2 ? key2s[ISDEVUNIT ? 1 : 0] : key1s[ISDEVUNIT ? 1 : 0], AES_KEYNORMAL, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2016-09-20 14:29:26 +02:00
|
|
|
|
2017-05-20 02:08:25 +02:00
|
|
|
u8 arm9BinSlot = k9lVersion == 0 ? 0x15 : 0x16;
|
2016-10-10 01:34:53 +02:00
|
|
|
|
2018-05-24 00:55:38 +02:00
|
|
|
// Get size
|
|
|
|
u32 arm9SectionSize = 0;
|
|
|
|
for(u32 i = 0; i < 8; i++)
|
|
|
|
arm9SectionSize = (arm9Section->size[i] - '0') + 10*arm9SectionSize;
|
|
|
|
|
2017-05-20 02:08:25 +02:00
|
|
|
//Set keyX
|
|
|
|
__attribute__((aligned(4))) u8 keyX[AES_BLOCK_SIZE];
|
|
|
|
aes_use_keyslot(0x11);
|
|
|
|
aes(keyX, k9lVersion == 0 ? arm9Section->keyX : arm9Section->slot0x16keyX, 1, NULL, AES_ECB_DECRYPT_MODE, 0);
|
|
|
|
aes_setkey(arm9BinSlot, keyX, AES_KEYX, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2017-04-14 17:05:25 +02:00
|
|
|
|
2017-05-20 02:08:25 +02:00
|
|
|
//Set keyY
|
|
|
|
__attribute__((aligned(4))) u8 keyY[AES_BLOCK_SIZE];
|
|
|
|
memcpy(keyY, arm9Section->keyY, sizeof(keyY));
|
|
|
|
aes_setkey(arm9BinSlot, keyY, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2017-04-13 02:49:19 +02:00
|
|
|
|
2017-05-20 02:08:25 +02:00
|
|
|
//Set CTR
|
|
|
|
__attribute__((aligned(4))) u8 arm9BinCtr[AES_BLOCK_SIZE];
|
|
|
|
memcpy(arm9BinCtr, arm9Section->ctr, sizeof(arm9BinCtr));
|
2017-04-14 17:05:25 +02:00
|
|
|
|
2017-05-20 02:08:25 +02:00
|
|
|
//Decrypt ARM9 binary
|
|
|
|
aes_use_keyslot(arm9BinSlot);
|
2018-05-24 00:55:38 +02:00
|
|
|
aes(startOfArm9Bin, startOfArm9Bin, arm9SectionSize / AES_BLOCK_SIZE, arm9BinCtr, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
2017-05-18 01:07:29 +02:00
|
|
|
|
2017-05-20 02:08:25 +02:00
|
|
|
if(*startOfArm9Bin != 0x47704770 && *startOfArm9Bin != 0xB0862000) error("Failed to decrypt the ARM9 binary.");
|
2016-08-03 14:13:26 +02:00
|
|
|
}
|
|
|
|
|
2016-09-20 14:19:33 +02:00
|
|
|
void computePinHash(u8 *outbuf, const u8 *inbuf)
|
2016-08-03 14:13:26 +02:00
|
|
|
{
|
2016-11-11 18:31:38 +01:00
|
|
|
__attribute__((aligned(4))) u8 cid[AES_BLOCK_SIZE],
|
|
|
|
cipherText[AES_BLOCK_SIZE];
|
2016-08-03 14:13:26 +02:00
|
|
|
|
2016-09-04 00:36:39 +02:00
|
|
|
sdmmc_get_cid(1, (u32 *)cid);
|
2016-11-12 01:49:52 +01:00
|
|
|
aes_use_keyslot(0x04); //Console-unique keyslot whose keys are set by the ARM9 bootROM
|
2016-09-20 15:16:19 +02:00
|
|
|
aes(cipherText, inbuf, 1, cid, AES_CBC_ENCRYPT_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
|
|
|
|
sha(outbuf, cipherText, sizeof(cipherText), SHA_256_MODE);
|
2016-09-22 14:48:28 +02:00
|
|
|
}
|