Use DTCM for ctrNandWrite's buffer, crt0 changes, reboot patch changes
This commit is contained in:
TuxSH
parent
10f555b6fb
commit
d57d8aaae7
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@ -30,7 +30,8 @@ operation:
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.word 0
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start:
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cpsid aif
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@ Disable interrupts and switch to supervisor mode
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cpsid aif, #0x13
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@ Set the control register to reset default: everything disabled
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ldr r0, =0x54078
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@ -42,11 +43,10 @@ start:
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mov r0, #0xF
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mcr p15, 0, r0, c1, c0, 1
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@ Invalidate all caches, flush the prefetch buffer and DSB
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@ Invalidate both caches, flush the prefetch buffer then DSB
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 4
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mcr p15, 0, r0, c7, c5, 0
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mcr p15, 0, r0, c7, c6, 0
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mcr p15, 0, r0, c7, c7, 0
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mcr p15, 0, r0, c7, c10, 4
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@ Clear BSS
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@ -43,7 +43,7 @@ disableMpuAndJumpToEntrypoints:
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, #(1<<12) @ - instruction cache disable
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bic r0, #(1<<2) @ - data cache disable
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bic r0, #(1<<0) @ - mpu disable
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bic r0, #(1<<0) @ - MPU disable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Set the ARM11 entrypoint
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@ -2,15 +2,17 @@
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.arm.little
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argv_addr equ 0x27FFDF00
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fname_addr equ 0x27FFDF80
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low_tid_addr equ 0x27FFDFE0
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copy_launch_stub_addr equ 0x27FFE000
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copy_launch_stub_stack_top equ 0x01FFB800
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copy_launch_stub_stack_bottom equ 0x01FFA800
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copy_launch_stub_addr equ 0x01FF9000
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firm_addr equ 0x20001000
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firm_maxsize equ (copy_launch_stub_addr - 0x1000 - firm_addr)
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argv_addr equ (copy_launch_stub_stack_bottom - 0x100)
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fname_addr equ (copy_launch_stub_stack_bottom - 0x200)
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low_tid_addr equ (copy_launch_stub_stack_bottom - 0x300)
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firm_addr equ 0x20001000
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firm_maxsize equ 0x07FFF000
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arm11_entrypoint_addr equ 0x1FFFFFFC
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.create "build/reboot.bin", 0
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.arm
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; Interesting registers and locations to keep in mind, set just before this code is ran:
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@ -154,17 +156,13 @@ fname: .ascii "FILE"
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cmp r5, #3
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blo load_section_loop
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ldr r0, =arm11_entrypoint_addr
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ldr r1, [r4, #0x08]
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str r1, [r0]
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mov r0, #2 ; argc
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ldr r1, =argv_addr ; argv
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ldr r2, =0xBABE ; magic word
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ldr r5, =arm11_entrypoint_addr
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mov r5, #0x20000000
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ldr r6, [r4, #0x08]
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str r6, [r5]
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str r6, [r5, #-4] ; store arm11 entrypoint
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ldr lr, [r4, #0x0c]
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bx lr
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@ -379,8 +379,8 @@ int ctrNandRead(u32 sector, u32 sectorCount, u8 *outbuf)
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int ctrNandWrite(u32 sector, u32 sectorCount, const u8 *inbuf)
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{
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u8 *buffer = (u8 *)0x23000000;
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u32 bufferSize = 0xF00000;
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u8 *buffer = (u8 *)0xFFF00000;
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u32 bufferSize = 0x4000;
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__attribute__((aligned(4))) u8 tmpCtr[sizeof(nandCtr)];
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memcpy(tmpCtr, nandCtr, sizeof(nandCtr));
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@ -24,10 +24,10 @@
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.align 4
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.global _start
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_start:
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@ Disable interrupts
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mrs r4, cpsr
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@ Disable interrupts and switch to supervisor mode (also clear flags)
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mov r4, #0x13
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orr r4, #0x1C0
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msr cpsr_cx, r4
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msr cpsr_cxsf, r4
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mov r9, r0
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mov r10, r1
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@ -38,30 +38,34 @@ _start:
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@ Disable caches / MPU
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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bic r4, #(1<<16) @ - DTCM disable
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bic r4, #(1<<12) @ - instruction cache disable
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bic r4, #(1<<2) @ - data cache disable
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bic r4, #(1<<0) @ - mpu disable
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bic r4, #(1<<0) @ - MPU disable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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@ Flush caches
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bl flushEntireDCache
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bl flushEntireICache
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@ Invalidate both caches, discarding any data they may contain,
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@ then drain the write buffer
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mov r4, #0
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mcr p15, 0, r4, c7, c5, 0
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mcr p15, 0, r4, c7, c6, 0
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mcr p15, 0, r4, c7, c10, 4
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@ Give read/write access to all the memory regions
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ldr r0, =0x3333333
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Set MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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ldr r1, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r2, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r3, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r4, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r5, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r6, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r7, #0
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mov r8, #0x15
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ldr r1, =0xFFF0801B @ fff00000 16k | dtcm
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ldr r2, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r3, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r4, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r8, #0x29
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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@ -70,17 +74,22 @@ _start:
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 4
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 3, 5
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 3, 5
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 3, 5
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@ Set DTCM address and size to the default values
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ldr r1, =0xFFF0800A @ set DTCM address and size
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mcr p15, 0, r1, c9, c1, 0 @ set the dtcm Region Register
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@ Enable caches / MPU / ITCM
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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orr r0, r0, #(1<<18) @ - ITCM enable
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orr r0, r0, #(1<<16) @ - DTCM enable
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orr r0, r0, #(1<<13) @ - alternate exception vectors enable
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orr r0, r0, #(1<<12) @ - instruction cache enable
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orr r0, r0, #(1<<2) @ - data cache enable
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orr r0, r0, #(1<<0) @ - mpu enable
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orr r0, r0, #(1<<0) @ - MPU enable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Clear BSS
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