169 lines
4.6 KiB
ArmAsm
169 lines
4.6 KiB
ArmAsm
@ This file is part of Luma3DS
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@ Copyright (C) 2016-2019 Aurora Wright, TuxSH
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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@
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@ Additional Terms 7.b and 7.c of GPLv3 apply to this file:
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@ * Requiring preservation of specified reasonable legal notices or
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@ author attributions in that material or in the Appropriate Legal
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@ Notices displayed by works containing it.
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@ * Prohibiting misrepresentation of the origin of that material,
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@ or requiring that modified versions of such material be marked in
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@ reasonable ways as different from the original version.
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.macro GEN_USUAL_HANDLER name, index
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\name\()Handler:
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ldr sp, =_regs
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stmia sp, {r0-r7}
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mov r0, #\index
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b _arm9ExceptionHandlerCommon
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.endm
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.section .arm9_exception_handlers.text, "ax", %progbits
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.arm
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.align 4
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.global _arm9ExceptionHandlerCommon
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.type _arm9ExceptionHandlerCommon, %function
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_arm9ExceptionHandlerCommon:
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mov r1, r0
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mov r0, sp
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mrs r2, spsr
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mrs r3, cpsr
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add r6, r0, #(8 * 4)
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orr r3, #0xc0 @ mask interrupts
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msr cpsr_cx, r3
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ands r4, r2, #0xf @ get the mode that triggered the exception
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moveq r4, #0xf @ usr => sys
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bic r5, r3, #0xf
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orr r5, r4
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msr cpsr_c, r5 @ change processor mode
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stmia r6!, {r8-lr}
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msr cpsr_c, r3 @ restore processor mode
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str lr, [r6], #4
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str r2, [r6]
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msr cpsr_cxsf, #0xdf @ finally, switch to system mode, mask interrupts and clear flags (in case of double faults)
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ldr sp, =0x02000000
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b arm9ExceptionHandlerMain
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.global FIQHandler
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.type FIQHandler, %function
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GEN_USUAL_HANDLER FIQ, 0
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.global undefinedInstructionHandler
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.type undefinedInstructionHandler, %function
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GEN_USUAL_HANDLER undefinedInstruction, 1
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.global prefetchAbortHandler
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.type prefetchAbortHandler, %function
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prefetchAbortHandler:
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msr cpsr_cx, #0xd7 @ mask interrupts (abort mode)
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mrs sp, spsr
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and sp, #0x3f
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cmp sp, #0x13
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bne _prefetchAbortNormalHandler
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ldr sp, =arm9ExceptionHandlerSvcBreakAddress
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ldr sp, [sp]
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cmp sp, #0
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beq _prefetchAbortNormalHandler
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add sp, #(1*4 + 4)
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cmp lr, sp
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bne _prefetchAbortNormalHandler
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mov sp, r8
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pop {r8-r11}
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ldr lr, [sp, #8]!
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ldr sp, [sp, #4]
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msr spsr_cxsf, sp
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tst sp, #0x20
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addne lr, #2 @ adjust address for later
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GEN_USUAL_HANDLER _prefetchAbortNormal, 2
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.global dataAbortHandler
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.type dataAbortHandler, %function
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dataAbortHandler:
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msr cpsr_cx, #0xd7 @ mask interrupts (abort mode)
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mrs sp, spsr
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and sp, #0x3f
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cmp sp, #0x1f
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bne _dataAbortNormalHandler
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sub lr, #8
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adr sp, safecpy
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cmp lr, sp
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blo _j_dataAbortNormalHandler
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adr sp, _safecpy_end
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cmp lr, sp
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bhs _j_dataAbortNormalHandler
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msr spsr_f, #(1 << 30)
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mov r12, #0
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adds pc, lr, #4
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_j_dataAbortNormalHandler:
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add lr, #8
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GEN_USUAL_HANDLER _dataAbortNormal, 3
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.global safecpy
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.type safecpy, %function
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safecpy:
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push {r4, lr}
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mov r3, #0
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movs r12, #1
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_safecpy_loop:
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ldrb r4, [r1, r3]
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cmp r12, #0
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beq _safecpy_loop_end
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strb r4, [r0, r3]
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add r3, #1
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cmp r3, r2
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blo _safecpy_loop
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_safecpy_loop_end:
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mov r0, r3
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pop {r4, pc}
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_safecpy_end:
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.section .arm9_exception_handlers.rodata, "a", %progbits
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.align 4
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.global arm9ExceptionHandlerAddressTable
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arm9ExceptionHandlerAddressTable:
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.word 0 @ IRQ
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.word FIQHandler @ FIQ
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.word 0 @ SVC
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.word undefinedInstructionHandler @ Undefined instruction
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.word prefetchAbortHandler @ Prefetch abort
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.word dataAbortHandler @ Data abort
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.section .arm9_exception_handlers.bss, "w", %nobits
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.align 4
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.global arm9ExceptionHandlerSvcBreakAddress
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arm9ExceptionHandlerSvcBreakAddress:
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.word 0
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_regs: .skip (4 * 17)
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