LowLevel/Luma3DS-3GX
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Setting "Dev. Options" to "None" no longer disable exception handling and related patches.

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Removed the patch that disables execution protection on the global kernel FCRAM and VRAM mapping as it was unused, worthless, and caused bugs in the past.
This commit is contained in:
TuxSH 2016-08-13 15:31:08 +02:00
parent 25811e2b52
commit 88891ef6cd
5 changed files with 29 additions and 55 deletions
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2
source/config.h
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@ -28,7 +28,7 @@
#define MULTICONFIG(a) ((config >> (a * 2 + 6)) & 3) #define MULTICONFIG(a) ((config >> (a * 2 + 6)) & 3)
#define BOOTCONFIG(a, b) ((config >> a) & b) #define BOOTCONFIG(a, b) ((config >> a) & b)
#define DEVMODE MULTICONFIG(2) #define DEV_OPTIONS MULTICONFIG(2)
extern u32 config; extern u32 config;

69
source/firm.c
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@ -76,11 +76,8 @@ void main(void)
//Attempt to read the configuration file //Attempt to read the configuration file
needConfig = fileRead(&config, configPath) ? MODIFY_CONFIGURATION : CREATE_CONFIGURATION; needConfig = fileRead(&config, configPath) ? MODIFY_CONFIGURATION : CREATE_CONFIGURATION;
if(DEVMODE) detectAndProcessExceptionDumps();
{ installArm9Handlers();
detectAndProcessExceptionDumps();
installArm9Handlers();
}
//Determine if this is a firmlaunch boot //Determine if this is a firmlaunch boot
if(*(vu8 *)0x23F00005) if(*(vu8 *)0x23F00005)
@ -345,30 +342,24 @@ static inline void patchNativeFirm(u32 firmVersion, FirmwareSource nandType, u32
reimplementSvcBackdoor(arm11Section1, section[1].size); reimplementSvcBackdoor(arm11Section1, section[1].size);
} }
if(DEVMODE) //Apply UNITINFO patch
{ if(DEV_OPTIONS == 2) patchUnitInfoValueSet(arm9Section, section[2].size);
//Apply UNITINFO patch
if(DEVMODE == 2) patchUnitInfoValueSet(arm9Section, section[2].size); //Install arm11 exception handlers
u32 stackAddress, codeSetOffset;
//Install arm11 exception handlers u32 *exceptionsPage = getInfoForArm11ExceptionHandlers(arm11Section1, section[1].size, &stackAddress, &codeSetOffset);
u32 stackAddress, codeSetOffset; installArm11Handlers(exceptionsPage, stackAddress, codeSetOffset);
u32 *exceptionsPage = getInfoForArm11ExceptionHandlers(arm11Section1, section[1].size, &stackAddress, &codeSetOffset);
installArm11Handlers(exceptionsPage, stackAddress, codeSetOffset); //Kernel9/Process9 debugging
patchExceptionHandlersInstall(arm9Section, section[2].size);
//Kernel9/Process9 debugging patchSvcBreak9(arm9Section, section[2].size, (u32)(section[2].address));
patchExceptionHandlersInstall(arm9Section, section[2].size); patchKernel9Panic(arm9Section, section[2].size, NATIVE_FIRM);
patchSvcBreak9(arm9Section, section[2].size, (u32)(section[2].address));
patchKernel9Panic(arm9Section, section[2].size, NATIVE_FIRM); //Stub svcBreak11 with "bkpt 65535"
patchSvcBreak11(arm11Section1, section[1].size);
//Stub svcBreak11 with "bkpt 65535" //Stub kernel11panic with "bkpt 65534"
patchSvcBreak11(arm11Section1, section[1].size); patchKernel11Panic(arm11Section1, section[1].size);
//Stub kernel11panic with "bkpt 65534"
patchKernel11Panic(arm11Section1, section[1].size);
//Make FCRAM (and VRAM as a side effect) globally executable from arm11 kernel
patchKernelFCRAMAndVRAMMappingPermissions(arm11Section1, section[1].size);
}
if(CONFIG(8)) if(CONFIG(8))
{ {
patchArm11SvcAccessChecks(arm11Section1, section[1].size); patchArm11SvcAccessChecks(arm11Section1, section[1].size);
@ -388,13 +379,10 @@ static inline void patchLegacyFirm(FirmwareType firmType)
firm->arm9Entry = (u8 *)0x801301C; firm->arm9Entry = (u8 *)0x801301C;
} }
if(DEVMODE) //Kernel9/Process9 debugging
{ patchExceptionHandlersInstall(arm9Section, section[3].size);
//Kernel9/Process9 debugging patchSvcBreak9(arm9Section, section[3].size, (u32)(section[3].address));
patchExceptionHandlersInstall(arm9Section, section[3].size); patchKernel9Panic(arm9Section, section[3].size, firmType);
patchSvcBreak9(arm9Section, section[3].size, (u32)(section[3].address));
patchKernel9Panic(arm9Section, section[3].size, firmType);
}
applyLegacyFirmPatches((u8 *)firm, firmType); applyLegacyFirmPatches((u8 *)firm, firmType);
} }
@ -413,12 +401,9 @@ static inline void patchSafeFirm(void)
} }
else patchFirmWriteSafe(arm9Section, section[2].size); else patchFirmWriteSafe(arm9Section, section[2].size);
if(DEVMODE) //Kernel9/Process9 debugging
{ patchExceptionHandlersInstall(arm9Section, section[2].size);
//Kernel9/Process9 debugging patchSvcBreak9(arm9Section, section[2].size, (u32)(section[2].address));
patchExceptionHandlersInstall(arm9Section, section[2].size);
patchSvcBreak9(arm9Section, section[2].size, (u32)(section[2].address));
}
} }
static inline void copySection0AndInjectSystemModules(FirmwareType firmType) static inline void copySection0AndInjectSystemModules(FirmwareType firmType)

11
source/patches.c
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@ -291,17 +291,6 @@ void patchUnitInfoValueSet(u8 *pos, u32 size)
off[3] = 0xE3; off[3] = 0xE3;
} }
void patchKernelFCRAMAndVRAMMappingPermissions(u8 *pos, u32 size)
{
//Look for MMU config
const u8 pattern[] = {0x97, 0x05, 0x00, 0x00, 0x15, 0xE4, 0x00, 0x00};
u32 *off = (u32 *)memsearch(pos, pattern, size, 8);
while(off != NULL && *off != 0x16416) off--;
if(off != NULL) *off &= ~(1 << 4); //Clear XN bit
}
void reimplementSvcBackdoor(u8 *pos, u32 size) void reimplementSvcBackdoor(u8 *pos, u32 size)
{ {
//Official implementation of svcBackdoor //Official implementation of svcBackdoor

1
source/patches.h
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@ -51,7 +51,6 @@ void patchArm11SvcAccessChecks(u8 *pos, u32 size);
void patchK11ModuleChecks(u8 *pos, u32 size); void patchK11ModuleChecks(u8 *pos, u32 size);
void patchP9AccessChecks(u8 *pos, u32 size); void patchP9AccessChecks(u8 *pos, u32 size);
void patchUnitInfoValueSet(u8 *pos, u32 size); void patchUnitInfoValueSet(u8 *pos, u32 size);
void patchKernelFCRAMAndVRAMMappingPermissions(u8 *pos, u32 size);
void reimplementSvcBackdoor(u8 *pos, u32 size); void reimplementSvcBackdoor(u8 *pos, u32 size);
void applyLegacyFirmPatches(u8 *pos, FirmwareType firmType); void applyLegacyFirmPatches(u8 *pos, FirmwareType firmType);
u8 *getUnitInfoValueSet(u8 *pos, u32 size); u8 *getUnitInfoValueSet(u8 *pos, u32 size);

1
source/start.s
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@ -72,6 +72,7 @@ start:
@ Enable caches / MPU @ Enable caches / MPU
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
orr r0, r0, #(1<<13) @ - alternate exception vectors enable
orr r0, r0, #(1<<12) @ - instruction cache enable orr r0, r0, #(1<<12) @ - instruction cache enable
orr r0, r0, #(1<<2) @ - data cache enable orr r0, r0, #(1<<2) @ - data cache enable
orr r0, r0, #(1<<0) @ - mpu enable orr r0, r0, #(1<<0) @ - mpu enable