Revert sdmmc driver, fixes regression #1225. Also fix a logic bug
This commit is contained in:
TuxSH
parent
8ff5111e30
commit
3d2c12cf09
@ -2,4 +2,4 @@
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#include "../../types.h"
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void wait_cycles(u32 us);
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void waitcycles(u32 us);
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16
source/fatfs/sdmmc/delay.s
Normal file
16
source/fatfs/sdmmc/delay.s
Normal file
@ -0,0 +1,16 @@
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.text
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.arm
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.align 4
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.global waitcycles
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.type waitcycles, %function
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waitcycles:
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push {r0-r2, lr}
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str r0, [sp, #4]
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waitcycles_loop:
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ldr r3, [sp, #4]
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subs r2, r3, #1
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str r2, [sp, #4]
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cmp r3, #0
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bne waitcycles_loop
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pop {r0-r2, pc}
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@ -1,6 +1,6 @@
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/*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this file,
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* License, v. 2.0. If a copy of the MPL was not distributed with this file,
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* You can obtain one at http://mozilla.org/MPL/2.0/.
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*
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* Copyright (c) 2014-2015, Normmatt
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@ -22,189 +22,143 @@
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* along with this program. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include "wait_cycles.h"
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#include "sdmmc.h"
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#include "delay.h"
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#define DATA32_SUPPORT
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static struct mmcdevice handleNAND;
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static struct mmcdevice handleSD;
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static inline u16 sdmmc_read16(u16 reg)
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{
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return *(vu16 *)(SDMMC_BASE + reg);
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}
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struct mmcdevice handleNAND;
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struct mmcdevice handleSD;
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static inline void sdmmc_write16(u16 reg, u16 val)
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{
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*(vu16 *)(SDMMC_BASE + reg) = val;
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}
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static inline u32 sdmmc_read32(u16 reg)
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{
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return *(vu32 *)(SDMMC_BASE + reg);
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}
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static inline void sdmmc_write32(u16 reg, u32 val)
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{
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*(vu32 *)(SDMMC_BASE + reg) = val;
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}
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static inline void sdmmc_mask16(u16 reg, const u16 clear, const u16 set)
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{
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u16 val = sdmmc_read16(reg);
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val &= ~clear;
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val |= set;
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sdmmc_write16(reg, val);
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}
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static inline void setckl(u32 data)
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{
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sdmmc_mask16(REG_SDCLKCTL, 0x100, 0);
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sdmmc_mask16(REG_SDCLKCTL, 0x2FF, data & 0x2FF);
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sdmmc_mask16(REG_SDCLKCTL, 0x0, 0x100);
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}
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mmcdevice *getMMCDevice(int drive)
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{
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if(drive==0) return &handleNAND;
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if(drive == 0) return &handleNAND;
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return &handleSD;
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}
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static int get_error(struct mmcdevice *ctx)
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static int geterror(struct mmcdevice *ctx)
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{
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return (int)((ctx->error << 29) >> 31);
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}
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static void set_target(struct mmcdevice *ctx)
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static void inittarget(struct mmcdevice *ctx)
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{
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sdmmc_mask16(REG_SDPORTSEL,0x3,(u16)ctx->devicenumber);
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sdmmc_mask16(REG_SDPORTSEL, 0x3, (u16)ctx->devicenumber);
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setckl(ctx->clk);
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if(ctx->SDOPT == 0)
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{
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sdmmc_mask16(REG_SDOPT,0,0x8000);
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}
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else
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{
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sdmmc_mask16(REG_SDOPT,0x8000,0);
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}
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if(ctx->SDOPT == 0) sdmmc_mask16(REG_SDOPT, 0, 0x8000);
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else sdmmc_mask16(REG_SDOPT, 0x8000, 0);
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}
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static void sdmmc_send_command(struct mmcdevice *ctx, u32 cmd, u32 args)
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static void __attribute__((noinline)) sdmmc_send_command(struct mmcdevice *ctx, u32 cmd, u32 args)
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{
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const bool getSDRESP = (cmd << 15) >> 31;
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u32 getSDRESP = (cmd << 15) >> 31;
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u16 flags = (cmd << 15) >> 31;
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const bool readdata = cmd & 0x20000;
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const bool writedata = cmd & 0x40000;
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const int readdata = cmd & 0x20000;
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const int writedata = cmd & 0x40000;
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if(readdata || writedata)
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{
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flags |= TMIO_STAT0_DATAEND;
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}
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ctx->error = 0;
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while((sdmmc_read16(REG_SDSTATUS1) & TMIO_STAT1_CMD_BUSY)); //mmc working?
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sdmmc_write16(REG_SDIRMASK0,0);
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sdmmc_write16(REG_SDIRMASK1,0);
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sdmmc_write16(REG_SDSTATUS0,0);
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sdmmc_write16(REG_SDSTATUS1,0);
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sdmmc_mask16(REG_DATACTL32,0x1800,0x400); // Disable TX32RQ and RX32RDY IRQ. Clear fifo.
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sdmmc_write16(REG_SDCMDARG0,args &0xFFFF);
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sdmmc_write16(REG_SDCMDARG1,args >> 16);
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sdmmc_write16(REG_SDCMD,cmd &0xFFFF);
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sdmmc_write16(REG_SDIRMASK0, 0);
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sdmmc_write16(REG_SDIRMASK1, 0);
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sdmmc_write16(REG_SDSTATUS0, 0);
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sdmmc_write16(REG_SDSTATUS1, 0);
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sdmmc_mask16(REG_DATACTL32, 0x1800, 0);
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sdmmc_write16(REG_SDCMDARG0, args & 0xFFFF);
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sdmmc_write16(REG_SDCMDARG1, args >> 16);
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sdmmc_write16(REG_SDCMD, cmd & 0xFFFF);
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u32 size = ctx->size;
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const u16 blkSize = sdmmc_read16(REG_SDBLKLEN32);
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u32 *rDataPtr32 = (u32*)(void*)ctx->rData;
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u8 *rDataPtr8 = ctx->rData;
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const u32 *tDataPtr32 = (u32*)(void*)ctx->tData;
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const u8 *tDataPtr8 = ctx->tData;
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u8 *rDataPtr = ctx->rData;
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const u8 *tDataPtr = ctx->tData;
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bool rUseBuf = ( NULL != rDataPtr32 );
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bool tUseBuf = ( NULL != tDataPtr32 );
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bool rUseBuf = rDataPtr != NULL;
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bool tUseBuf = tDataPtr != NULL;
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u16 status0 = 0;
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while(1)
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while(true)
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{
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volatile u16 status1 = sdmmc_read16(REG_SDSTATUS1);
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#ifdef DATA32_SUPPORT
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volatile u16 ctl32 = sdmmc_read16(REG_DATACTL32);
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vu16 status1 = sdmmc_read16(REG_SDSTATUS1);
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vu16 ctl32 = sdmmc_read16(REG_DATACTL32);
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if((ctl32 & 0x100))
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#else
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if((status1 & TMIO_STAT1_RXRDY))
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#endif
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{
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if(readdata)
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{
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if(rUseBuf)
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{
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sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_RXRDY, 0);
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if(size >= blkSize)
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if(size > 0x1FF)
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{
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#ifdef DATA32_SUPPORT
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if(!((u32)rDataPtr32 & 3))
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//Gabriel Marcano: This implementation doesn't assume alignment.
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//I've removed the alignment check doen with former rUseBuf32 as a result
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for(int i = 0; i < 0x200; i += 4)
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{
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for(u32 i = 0; i < blkSize; i += 4)
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{
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*rDataPtr32++ = sdmmc_read32(REG_SDFIFO32);
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}
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u32 data = sdmmc_read32(REG_SDFIFO32);
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*rDataPtr++ = data;
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*rDataPtr++ = data >> 8;
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*rDataPtr++ = data >> 16;
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*rDataPtr++ = data >> 24;
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}
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else
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{
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for(u32 i = 0; i < blkSize; i += 4)
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{
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u32 data = sdmmc_read32(REG_SDFIFO32);
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*rDataPtr8++ = data;
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*rDataPtr8++ = data >> 8;
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*rDataPtr8++ = data >> 16;
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*rDataPtr8++ = data >> 24;
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}
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}
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#else
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if(!((u32)rDataPtr16 & 1))
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{
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for(u32 i = 0; i < blkSize; i += 4)
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{
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*rDataPtr16++ = sdmmc_read16(REG_SDFIFO);
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}
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}
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else
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{
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for(u32 i = 0; i < blkSize; i += 4)
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{
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u16 data = sdmmc_read16(REG_SDFIFO);
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*rDataPtr8++ = data;
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*rDataPtr8++ = data >> 8;
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}
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}
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#endif
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size -= blkSize;
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size -= 0x200;
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}
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}
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sdmmc_mask16(REG_DATACTL32, 0x800, 0);
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}
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}
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#ifdef DATA32_SUPPORT
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if(!(ctl32 & 0x200))
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#else
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if((status1 & TMIO_STAT1_TXRQ))
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#endif
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{
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if(writedata)
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{
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if(tUseBuf)
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{
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sdmmc_mask16(REG_SDSTATUS1, TMIO_STAT1_TXRQ, 0);
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if(size >= blkSize)
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if(size > 0x1FF)
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{
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#ifdef DATA32_SUPPORT
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if(!((u32)tDataPtr32 & 3))
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for(int i = 0; i < 0x200; i += 4)
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{
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for(u32 i = 0; i < blkSize; i += 4)
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{
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sdmmc_write32(REG_SDFIFO32, *tDataPtr32++);
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}
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u32 data = *tDataPtr++;
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data |= (u32)*tDataPtr++ << 8;
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data |= (u32)*tDataPtr++ << 16;
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data |= (u32)*tDataPtr++ << 24;
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sdmmc_write32(REG_SDFIFO32, data);
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}
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else
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{
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for(u32 i = 0; i < blkSize; i += 4)
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{
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u32 data = *tDataPtr8++;
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data |= (u32)*tDataPtr8++ << 8;
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data |= (u32)*tDataPtr8++ << 16;
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data |= (u32)*tDataPtr8++ << 24;
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sdmmc_write32(REG_SDFIFO32, data);
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}
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}
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#else
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if(!((u32)tDataPtr16 & 1))
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{
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for(u32 i = 0; i < blkSize; i += 2)
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{
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sdmmc_write16(REG_SDFIFO, *tDataPtr16++);
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}
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}
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else
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{
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for(u32 i = 0; i < blkSize; i += 2)
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{
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u16 data = *tDataPtr8++;
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data |= (u16)(*tDataPtr8++ << 8);
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sdmmc_write16(REG_SDFIFO, data);
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}
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}
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#endif
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size -= blkSize;
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size -= 0x200;
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}
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}
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@ -235,8 +189,8 @@ static void sdmmc_send_command(struct mmcdevice *ctx, u32 cmd, u32 args)
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}
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ctx->stat0 = sdmmc_read16(REG_SDSTATUS0);
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ctx->stat1 = sdmmc_read16(REG_SDSTATUS1);
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sdmmc_write16(REG_SDSTATUS0,0);
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sdmmc_write16(REG_SDSTATUS1,0);
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sdmmc_write16(REG_SDSTATUS0, 0);
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sdmmc_write16(REG_SDSTATUS1, 0);
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if(getSDRESP != 0)
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{
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@ -247,243 +201,213 @@ static void sdmmc_send_command(struct mmcdevice *ctx, u32 cmd, u32 args)
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}
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}
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int sdmmc_sdcard_writesectors(u32 sector_no, u32 numsectors, const u8 *in)
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int __attribute__((noinline)) sdmmc_sdcard_writesectors(u32 sector_no, u32 numsectors, const u8 *in)
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{
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if(handleSD.isSDHC == 0) sector_no <<= 9;
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set_target(&handleSD);
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sdmmc_write16(REG_SDSTOP,0x100);
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#ifdef DATA32_SUPPORT
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sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
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sdmmc_write16(REG_SDBLKLEN32,0x200);
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#endif
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sdmmc_write16(REG_SDBLKCOUNT,numsectors);
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inittarget(&handleSD);
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sdmmc_write16(REG_SDSTOP, 0x100);
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sdmmc_write16(REG_SDBLKCOUNT32, numsectors);
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sdmmc_write16(REG_SDBLKLEN32, 0x200);
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sdmmc_write16(REG_SDBLKCOUNT, numsectors);
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handleSD.tData = in;
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handleSD.size = numsectors << 9;
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sdmmc_send_command(&handleSD,0x52C19,sector_no);
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return get_error(&handleSD);
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sdmmc_send_command(&handleSD, 0x52C19, sector_no);
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return geterror(&handleSD);
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}
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int sdmmc_sdcard_readsectors(u32 sector_no, u32 numsectors, u8 *out)
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int __attribute__((noinline)) sdmmc_sdcard_readsectors(u32 sector_no, u32 numsectors, u8 *out)
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{
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if(handleSD.isSDHC == 0) sector_no <<= 9;
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set_target(&handleSD);
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sdmmc_write16(REG_SDSTOP,0x100);
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#ifdef DATA32_SUPPORT
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sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
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sdmmc_write16(REG_SDBLKLEN32,0x200);
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#endif
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sdmmc_write16(REG_SDBLKCOUNT,numsectors);
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inittarget(&handleSD);
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sdmmc_write16(REG_SDSTOP, 0x100);
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sdmmc_write16(REG_SDBLKCOUNT32, numsectors);
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sdmmc_write16(REG_SDBLKLEN32, 0x200);
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sdmmc_write16(REG_SDBLKCOUNT, numsectors);
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handleSD.rData = out;
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handleSD.size = numsectors << 9;
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sdmmc_send_command(&handleSD,0x33C12,sector_no);
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return get_error(&handleSD);
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sdmmc_send_command(&handleSD, 0x33C12, sector_no);
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return geterror(&handleSD);
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}
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int sdmmc_nand_readsectors(u32 sector_no, u32 numsectors, u8 *out)
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int __attribute__((noinline)) sdmmc_nand_readsectors(u32 sector_no, u32 numsectors, u8 *out)
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{
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if(handleNAND.isSDHC == 0) sector_no <<= 9;
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set_target(&handleNAND);
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sdmmc_write16(REG_SDSTOP,0x100);
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#ifdef DATA32_SUPPORT
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sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
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sdmmc_write16(REG_SDBLKLEN32,0x200);
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#endif
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sdmmc_write16(REG_SDBLKCOUNT,numsectors);
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inittarget(&handleNAND);
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sdmmc_write16(REG_SDSTOP, 0x100);
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sdmmc_write16(REG_SDBLKCOUNT32, numsectors);
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sdmmc_write16(REG_SDBLKLEN32, 0x200);
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sdmmc_write16(REG_SDBLKCOUNT, numsectors);
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handleNAND.rData = out;
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handleNAND.size = numsectors << 9;
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sdmmc_send_command(&handleNAND,0x33C12,sector_no);
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return get_error(&handleNAND);
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sdmmc_send_command(&handleNAND, 0x33C12, sector_no);
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inittarget(&handleSD);
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return geterror(&handleNAND);
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}
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int sdmmc_nand_writesectors(u32 sector_no, u32 numsectors, const u8 *in) //experimental
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int __attribute__((noinline)) sdmmc_nand_writesectors(u32 sector_no, u32 numsectors, const u8 *in) //experimental
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{
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if(handleNAND.isSDHC == 0) sector_no <<= 9;
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set_target(&handleNAND);
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sdmmc_write16(REG_SDSTOP,0x100);
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#ifdef DATA32_SUPPORT
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sdmmc_write16(REG_SDBLKCOUNT32,numsectors);
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sdmmc_write16(REG_SDBLKLEN32,0x200);
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#endif
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sdmmc_write16(REG_SDBLKCOUNT,numsectors);
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inittarget(&handleNAND);
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sdmmc_write16(REG_SDSTOP, 0x100);
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sdmmc_write16(REG_SDBLKCOUNT32, numsectors);
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sdmmc_write16(REG_SDBLKLEN32, 0x200);
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sdmmc_write16(REG_SDBLKCOUNT, numsectors);
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handleNAND.tData = in;
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handleNAND.size = numsectors << 9;
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sdmmc_send_command(&handleNAND,0x52C19,sector_no);
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return get_error(&handleNAND);
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sdmmc_send_command(&handleNAND, 0x52C19, sector_no);
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inittarget(&handleSD);
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return geterror(&handleNAND);
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}
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static u32 sdmmc_calc_size(u8* csd, int type)
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static u32 calcSDSize(u8 *csd, int type)
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{
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u32 result = 0;
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if(type == -1) type = csd[14] >> 6;
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switch(type)
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{
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case 0:
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{
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u32 block_len=csd[9]&0xf;
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block_len=1u<<block_len;
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u32 mult=( u32)((csd[4]>>7)|((csd[5]&3)<<1));
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mult=1u<<(mult+2);
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result=csd[8]&3;
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result=(result<<8)|csd[7];
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result=(result<<2)|(csd[6]>>6);
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result=(result+1)*mult*block_len/512;
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}
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break;
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case 1:
|
||||
result=csd[7]&0x3f;
|
||||
result=(result<<8)|csd[6];
|
||||
result=(result<<8)|csd[5];
|
||||
result=(result+1)*1024;
|
||||
break;
|
||||
default:
|
||||
break; //Do nothing otherwise FIXME perhaps return some error?
|
||||
}
|
||||
return result;
|
||||
u32 result = 0;
|
||||
if(type == -1) type = csd[14] >> 6;
|
||||
switch(type)
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
u32 block_len = csd[9] & 0xF;
|
||||
block_len = 1u << block_len;
|
||||
u32 mult = (u32)((csd[4] >> 7) | ((csd[5] & 3) << 1));
|
||||
mult = 1u << (mult + 2);
|
||||
result = csd[8] & 3;
|
||||
result = (result << 8) | csd[7];
|
||||
result = (result << 2) | (csd[6] >> 6);
|
||||
result = (result + 1) * mult * block_len / 512;
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
result = csd[7] & 0x3F;
|
||||
result = (result << 8) | csd[6];
|
||||
result = (result << 8) | csd[5];
|
||||
result = (result + 1) * 1024;
|
||||
break;
|
||||
default:
|
||||
break; //Do nothing otherwise FIXME perhaps return some error?
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
void sdmmc_init()
|
||||
static void InitSD()
|
||||
{
|
||||
*(vu32 *)0x10000020 = 0; //InitFS stuff
|
||||
*(vu32 *)0x10000020 = 0x200; //InitFS stuff
|
||||
*(vu16 *)0x10006100 &= 0xF7FFu; //SDDATACTL32
|
||||
*(vu16 *)0x10006100 &= 0xEFFFu; //SDDATACTL32
|
||||
*(vu16 *)0x10006100 |= 0x402u; //SDDATACTL32
|
||||
*(vu16 *)0x100060D8 = (*(vu16 *)0x100060D8 & 0xFFDD) | 2;
|
||||
*(vu16 *)0x10006100 &= 0xFFFFu; //SDDATACTL32
|
||||
*(vu16 *)0x100060D8 &= 0xFFDFu; //SDDATACTL
|
||||
*(vu16 *)0x10006104 = 512; //SDBLKLEN32
|
||||
*(vu16 *)0x10006108 = 1; //SDBLKCOUNT32
|
||||
*(vu16 *)0x100060E0 &= 0xFFFEu; //SDRESET
|
||||
*(vu16 *)0x100060E0 |= 1u; //SDRESET
|
||||
*(vu16 *)0x10006020 |= TMIO_MASK_ALL; //SDIR_MASK0
|
||||
*(vu16 *)0x10006022 |= TMIO_MASK_ALL>>16; //SDIR_MASK1
|
||||
*(vu16 *)0x100060FC |= 0xDBu; //SDCTL_RESERVED7
|
||||
*(vu16 *)0x100060FE |= 0xDBu; //SDCTL_RESERVED8
|
||||
*(vu16 *)0x10006002 &= 0xFFFCu; //SDPORTSEL
|
||||
*(vu16 *)0x10006024 = 0x20;
|
||||
*(vu16 *)0x10006028 = 0x40EE;
|
||||
*(vu16 *)0x10006002 &= 0xFFFCu; ////SDPORTSEL
|
||||
*(vu16 *)0x10006026 = 512; //SDBLKLEN
|
||||
*(vu16 *)0x10006008 = 0; //SDSTOP
|
||||
}
|
||||
|
||||
static int Nand_Init()
|
||||
{
|
||||
//NAND
|
||||
handleNAND.isSDHC = 0;
|
||||
handleNAND.SDOPT = 0;
|
||||
handleNAND.res = 0;
|
||||
handleNAND.initarg = 1;
|
||||
handleNAND.clk = 0x20; // 523.655968 KHz
|
||||
handleNAND.clk = 0x80;
|
||||
handleNAND.devicenumber = 1;
|
||||
|
||||
inittarget(&handleNAND);
|
||||
waitcycles(0xF000);
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0, 0);
|
||||
|
||||
do
|
||||
{
|
||||
do
|
||||
{
|
||||
sdmmc_send_command(&handleNAND, 0x10701, 0x100000);
|
||||
}
|
||||
while(!(handleNAND.error & 1));
|
||||
}
|
||||
while((handleNAND.ret[0] & 0x80000000) == 0);
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x10602, 0x0);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x10403, handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x10609, handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
handleNAND.total_size = calcSDSize((u8*)&handleNAND.ret[0], 0);
|
||||
handleNAND.clk = 1;
|
||||
setckl(1);
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x10407, handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
handleNAND.SDOPT = 1;
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x10506, 0x3B70100);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x10506, 0x3B90100);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x1040D, handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND, 0x10410, 0x200);
|
||||
if((handleNAND.error & 0x4)) return -1;
|
||||
|
||||
handleNAND.clk |= 0x200;
|
||||
|
||||
inittarget(&handleSD);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int SD_Init()
|
||||
{
|
||||
//SD
|
||||
handleSD.isSDHC = 0;
|
||||
handleSD.SDOPT = 0;
|
||||
handleSD.res = 0;
|
||||
handleSD.initarg = 0;
|
||||
handleSD.clk = 0x20; // 523.655968 KHz
|
||||
handleSD.clk = 0x80;
|
||||
handleSD.devicenumber = 0;
|
||||
|
||||
*(vu16*)0x10006100 &= 0xF7FFu; //SDDATACTL32
|
||||
*(vu16*)0x10006100 &= 0xEFFFu; //SDDATACTL32
|
||||
#ifdef DATA32_SUPPORT
|
||||
*(vu16*)0x10006100 |= 0x402u; //SDDATACTL32
|
||||
#else
|
||||
*(vu16*)0x10006100 |= 0x402u; //SDDATACTL32
|
||||
#endif
|
||||
*(vu16*)0x100060D8 = (*(vu16*)0x100060D8 & 0xFFDD) | 2;
|
||||
#ifdef DATA32_SUPPORT
|
||||
*(vu16*)0x10006100 &= 0xFFFFu; //SDDATACTL32
|
||||
*(vu16*)0x100060D8 &= 0xFFDFu; //SDDATACTL
|
||||
*(vu16*)0x10006104 = 512; //SDBLKLEN32
|
||||
#else
|
||||
*(vu16*)0x10006100 &= 0xFFFDu; //SDDATACTL32
|
||||
*(vu16*)0x100060D8 &= 0xFFDDu; //SDDATACTL
|
||||
*(vu16*)0x10006104 = 0; //SDBLKLEN32
|
||||
#endif
|
||||
*(vu16*)0x10006108 = 1; //SDBLKCOUNT32
|
||||
*(vu16*)0x100060E0 &= 0xFFFEu; //SDRESET
|
||||
*(vu16*)0x100060E0 |= 1u; //SDRESET
|
||||
*(vu16*)0x10006020 |= TMIO_MASK_ALL; //SDIR_MASK0
|
||||
*(vu16*)0x10006022 |= TMIO_MASK_ALL>>16; //SDIR_MASK1
|
||||
*(vu16*)0x100060FC |= 0xDBu; //SDCTL_RESERVED7
|
||||
*(vu16*)0x100060FE |= 0xDBu; //SDCTL_RESERVED8
|
||||
*(vu16*)0x10006002 &= 0xFFFCu; //SDPORTSEL
|
||||
#ifdef DATA32_SUPPORT
|
||||
*(vu16*)0x10006024 = 0x20;
|
||||
*(vu16*)0x10006028 = 0x40E9;
|
||||
#else
|
||||
*(vu16*)0x10006024 = 0x40; //Nintendo sets this to 0x20
|
||||
*(vu16*)0x10006028 = 0x40E9; //Nintendo sets this to 0x40EE
|
||||
#endif
|
||||
*(vu16*)0x10006002 &= 0xFFFCu; ////SDPORTSEL
|
||||
*(vu16*)0x10006026 = 512; //SDBLKLEN
|
||||
*(vu16*)0x10006008 = 0; //SDSTOP
|
||||
}
|
||||
inittarget(&handleSD);
|
||||
|
||||
int Nand_Init()
|
||||
{
|
||||
// init the handle
|
||||
handleNAND.isSDHC = 0;
|
||||
handleNAND.SDOPT = 0;
|
||||
handleNAND.res = 0;
|
||||
handleNAND.initarg = 1;
|
||||
handleNAND.clk = 0x20; // 523.655968 KHz
|
||||
handleNAND.devicenumber = 1;
|
||||
waitcycles(1u << 22); //Card needs a little bit of time to be detected, it seems FIXME test again to see what a good number is for the delay
|
||||
|
||||
// The eMMC is always on. Nothing special to do.
|
||||
set_target(&handleNAND);
|
||||
//If not inserted
|
||||
if(!(*((vu16 *)(SDMMC_BASE + REG_SDSTATUS0)) & TMIO_STAT0_SIGSTATE)) return 5;
|
||||
|
||||
sdmmc_send_command(&handleNAND,0,0);
|
||||
|
||||
do
|
||||
{
|
||||
do
|
||||
{
|
||||
sdmmc_send_command(&handleNAND,0x10701,0x100000);
|
||||
} while ( !(handleNAND.error & 1) );
|
||||
}
|
||||
while((handleNAND.ret[0] & 0x80000000) == 0);
|
||||
|
||||
sdmmc_send_command(&handleNAND,0x10602,0x0);
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND,0x10403,handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND,0x10609,handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
|
||||
handleNAND.total_size = sdmmc_calc_size((u8*)&handleNAND.ret[0],0);
|
||||
setckl(0x201); // 16.756991 MHz
|
||||
|
||||
sdmmc_send_command(&handleNAND,0x10407,handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
|
||||
handleNAND.SDOPT = 1;
|
||||
sdmmc_send_command(&handleNAND,0x10506,0x3B70100); // Set 4 bit bus width.
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
sdmmc_mask16(REG_SDOPT, 0x8000, 0); // Switch to 4 bit mode.
|
||||
|
||||
sdmmc_send_command(&handleNAND,0x10506,0x3B90100); // Switch to high speed timing.
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
handleNAND.clk = 0x200; // 33.513982 MHz
|
||||
setckl(0x200);
|
||||
|
||||
sdmmc_send_command(&handleNAND,0x1040D,handleNAND.initarg << 0x10);
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
|
||||
sdmmc_send_command(&handleNAND,0x10410,0x200);
|
||||
if((handleNAND.error & 0x4))return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SD_Init()
|
||||
{
|
||||
// init the handle
|
||||
handleSD.isSDHC = 0;
|
||||
handleSD.SDOPT = 0;
|
||||
handleSD.res = 0;
|
||||
handleSD.initarg = 0;
|
||||
handleSD.clk = 0x20; // 523.655968 KHz
|
||||
handleSD.devicenumber = 0;
|
||||
|
||||
// We need to send at least 74 clock pulses.
|
||||
set_target(&handleSD);
|
||||
wait_cycles(0x1980); // ~75-76 clocks
|
||||
|
||||
sdmmc_send_command(&handleSD,0,0);
|
||||
sdmmc_send_command(&handleSD,0x10408,0x1AA);
|
||||
sdmmc_send_command(&handleSD, 0, 0);
|
||||
sdmmc_send_command(&handleSD, 0x10408, 0x1AA);
|
||||
u32 temp = (handleSD.error & 0x1) << 0x1E;
|
||||
|
||||
u32 temp2 = 0;
|
||||
|
||||
do
|
||||
{
|
||||
do
|
||||
{
|
||||
sdmmc_send_command(&handleSD,0x10437,handleSD.initarg << 0x10);
|
||||
sdmmc_send_command(&handleSD,0x10769,0x10100000 | temp); // Allow 150mA, 3.2-3.3V (from Process9)
|
||||
sdmmc_send_command(&handleSD, 0x10437, handleSD.initarg << 0x10);
|
||||
sdmmc_send_command(&handleSD, 0x10769, 0x00FF8000 | temp);
|
||||
temp2 = 1;
|
||||
} while ( !(handleSD.error & 1) );
|
||||
}
|
||||
while(!(handleSD.error & 1));
|
||||
}
|
||||
while((handleSD.ret[0] & 0x80000000) == 0);
|
||||
|
||||
@ -492,127 +416,67 @@ int SD_Init()
|
||||
|
||||
handleSD.isSDHC = temp2;
|
||||
|
||||
sdmmc_send_command(&handleSD,0x10602,0);
|
||||
sdmmc_send_command(&handleSD, 0x10602, 0);
|
||||
if((handleSD.error & 0x4)) return -1;
|
||||
|
||||
sdmmc_send_command(&handleSD,0x10403,0);
|
||||
sdmmc_send_command(&handleSD, 0x10403, 0);
|
||||
if((handleSD.error & 0x4)) return -2;
|
||||
handleSD.initarg = handleSD.ret[0] >> 0x10;
|
||||
|
||||
sdmmc_send_command(&handleSD,0x10609,handleSD.initarg << 0x10);
|
||||
sdmmc_send_command(&handleSD, 0x10609, handleSD.initarg << 0x10);
|
||||
if((handleSD.error & 0x4)) return -3;
|
||||
|
||||
// Command Class 10 support
|
||||
const bool cmd6Supported = ((u8*)handleSD.ret)[10] & 0x40;
|
||||
handleSD.total_size = sdmmc_calc_size((u8*)&handleSD.ret[0],-1);
|
||||
setckl(0x201); // 16.756991 MHz
|
||||
handleSD.total_size = calcSDSize((u8*)&handleSD.ret[0], -1);
|
||||
handleSD.clk = 1;
|
||||
setckl(1);
|
||||
|
||||
sdmmc_send_command(&handleSD,0x10507,handleSD.initarg << 0x10);
|
||||
sdmmc_send_command(&handleSD, 0x10507, handleSD.initarg << 0x10);
|
||||
if((handleSD.error & 0x4)) return -4;
|
||||
|
||||
// CMD55
|
||||
sdmmc_send_command(&handleSD,0x10437,handleSD.initarg << 0x10);
|
||||
if(handleSD.error & 0x4) return -5;
|
||||
|
||||
// ACMD42 SET_CLR_CARD_DETECT
|
||||
sdmmc_send_command(&handleSD,0x1076A,0x0);
|
||||
if(handleSD.error & 0x4) return -6;
|
||||
|
||||
sdmmc_send_command(&handleSD,0x10437,handleSD.initarg << 0x10);
|
||||
if((handleSD.error & 0x4)) return -7;
|
||||
sdmmc_send_command(&handleSD, 0x10437, handleSD.initarg << 0x10);
|
||||
if((handleSD.error & 0x4)) return -5;
|
||||
|
||||
handleSD.SDOPT = 1;
|
||||
sdmmc_send_command(&handleSD,0x10446,0x2);
|
||||
sdmmc_send_command(&handleSD, 0x10446, 0x2);
|
||||
if((handleSD.error & 0x4)) return -6;
|
||||
|
||||
sdmmc_send_command(&handleSD, 0x1040D, handleSD.initarg << 0x10);
|
||||
if((handleSD.error & 0x4)) return -7;
|
||||
|
||||
sdmmc_send_command(&handleSD, 0x10410, 0x200);
|
||||
if((handleSD.error & 0x4)) return -8;
|
||||
sdmmc_mask16(REG_SDOPT, 0x8000, 0); // Switch to 4 bit mode.
|
||||
|
||||
// TODO: CMD6 to switch to high speed mode.
|
||||
if(cmd6Supported)
|
||||
{
|
||||
sdmmc_write16(REG_SDSTOP,0);
|
||||
sdmmc_write16(REG_SDBLKLEN32,64);
|
||||
sdmmc_write16(REG_SDBLKLEN,64);
|
||||
handleSD.rData = NULL;
|
||||
handleSD.size = 64;
|
||||
sdmmc_send_command(&handleSD,0x31C06,0x80FFFFF1);
|
||||
sdmmc_write16(REG_SDBLKLEN,512);
|
||||
if(handleSD.error & 0x4) return -9;
|
||||
|
||||
handleSD.clk = 0x200; // 33.513982 MHz
|
||||
setckl(0x200);
|
||||
}
|
||||
else handleSD.clk = 0x201; // 16.756991 MHz
|
||||
|
||||
sdmmc_send_command(&handleSD,0x1040D,handleSD.initarg << 0x10);
|
||||
if((handleSD.error & 0x4)) return -9;
|
||||
|
||||
sdmmc_send_command(&handleSD,0x10410,0x200);
|
||||
if((handleSD.error & 0x4)) return -10;
|
||||
handleSD.clk |= 0x200;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sdmmc_get_cid(bool isNand, u32 *info)
|
||||
void sdmmc_get_cid(bool isNand, u32 *info)
|
||||
{
|
||||
struct mmcdevice *device;
|
||||
if(isNand)
|
||||
device = &handleNAND;
|
||||
else
|
||||
device = &handleSD;
|
||||
struct mmcdevice *device = isNand ? &handleNAND : &handleSD;
|
||||
|
||||
inittarget(device);
|
||||
|
||||
set_target(device);
|
||||
// use cmd7 to put sd card in standby mode
|
||||
// CMD7
|
||||
{
|
||||
sdmmc_send_command(device,0x10507,0);
|
||||
//if((device->error & 0x4)) return -1;
|
||||
}
|
||||
sdmmc_send_command(device, 0x10507, 0);
|
||||
|
||||
// get sd card info
|
||||
// use cmd10 to read CID
|
||||
{
|
||||
sdmmc_send_command(device,0x1060A,device->initarg << 0x10);
|
||||
//if((device->error & 0x4)) return -2;
|
||||
sdmmc_send_command(device, 0x1060A, device->initarg << 0x10);
|
||||
|
||||
for( int i = 0; i < 4; ++i ) {
|
||||
info[i] = device->ret[i];
|
||||
}
|
||||
}
|
||||
for(int i = 0; i < 4; ++i)
|
||||
info[i] = device->ret[i];
|
||||
|
||||
// put sd card back to transfer mode
|
||||
// CMD7
|
||||
{
|
||||
sdmmc_send_command(device,0x10507,device->initarg << 0x10);
|
||||
//if((device->error & 0x4)) return -3;
|
||||
}
|
||||
|
||||
return 0;
|
||||
sdmmc_send_command(device, 0x10507, device->initarg << 0x10);
|
||||
}
|
||||
|
||||
u32 sdmmc_sdcard_init()
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
// SD mount fix
|
||||
*((vu16*)0x10000020) = 0x340;
|
||||
|
||||
// init SDMMC / NAND
|
||||
sdmmc_init();
|
||||
if(Nand_Init() != 0) ret &= 1;
|
||||
|
||||
// init SDMMC / SDCARD
|
||||
u32 timeout = 20; // number of tries (2ms per try)
|
||||
|
||||
do {
|
||||
// if sd card is ready, stop polling
|
||||
if(sdmmc_read16(REG_SDSTATUS0) & TMIO_STAT0_SIGSTATE)
|
||||
break;
|
||||
|
||||
wait_cycles(268000000); // approx 2ms
|
||||
timeout--;
|
||||
} while(timeout);
|
||||
|
||||
if(!timeout || SD_Init() != 0) ret &= 2;
|
||||
|
||||
InitSD();
|
||||
if(Nand_Init() != 0) ret |= 1;
|
||||
if(SD_Init() != 0) ret |= 2;
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -1,182 +1,100 @@
|
||||
#pragma once
|
||||
|
||||
/*
|
||||
* This Source Code Form is subject to the terms of the Mozilla Public
|
||||
* License, v. 2.0. If a copy of the MPL was not distributed with this file,
|
||||
* You can obtain one at http://mozilla.org/MPL/2.0/.
|
||||
*
|
||||
* Copyright (c) 2014-2015, Normmatt
|
||||
*
|
||||
* Alternatively, the contents of this file may be used under the terms
|
||||
* of the GNU General Public License Version 2, as described below:
|
||||
*
|
||||
* This file is free software: you may copy, redistribute and/or modify
|
||||
* it under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation, either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
|
||||
* Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see http://www.gnu.org/licenses/.
|
||||
*/
|
||||
|
||||
#include "../../types.h"
|
||||
|
||||
#define SDMMC_BASE (0x10006000)
|
||||
#define SDMMC_BASE 0x10006000
|
||||
|
||||
#define REG_SDCMD (0x00)
|
||||
#define REG_SDPORTSEL (0x02)
|
||||
#define REG_SDCMDARG (0x04)
|
||||
#define REG_SDCMDARG0 (0x04)
|
||||
#define REG_SDCMDARG1 (0x06)
|
||||
#define REG_SDSTOP (0x08)
|
||||
#define REG_SDBLKCOUNT (0x0a)
|
||||
#define REG_SDCMD 0x00
|
||||
#define REG_SDPORTSEL 0x02
|
||||
#define REG_SDCMDARG 0x04
|
||||
#define REG_SDCMDARG0 0x04
|
||||
#define REG_SDCMDARG1 0x06
|
||||
#define REG_SDSTOP 0x08
|
||||
#define REG_SDBLKCOUNT 0x0A
|
||||
|
||||
#define REG_SDRESP0 (0x0c)
|
||||
#define REG_SDRESP1 (0x0e)
|
||||
#define REG_SDRESP2 (0x10)
|
||||
#define REG_SDRESP3 (0x12)
|
||||
#define REG_SDRESP4 (0x14)
|
||||
#define REG_SDRESP5 (0x16)
|
||||
#define REG_SDRESP6 (0x18)
|
||||
#define REG_SDRESP7 (0x1a)
|
||||
#define REG_SDRESP0 0x0C
|
||||
#define REG_SDRESP1 0x0E
|
||||
#define REG_SDRESP2 0x10
|
||||
#define REG_SDRESP3 0x12
|
||||
#define REG_SDRESP4 0x14
|
||||
#define REG_SDRESP5 0x16
|
||||
#define REG_SDRESP6 0x18
|
||||
#define REG_SDRESP7 0x1A
|
||||
|
||||
#define REG_SDSTATUS0 (0x1c)
|
||||
#define REG_SDSTATUS1 (0x1e)
|
||||
#define REG_SDSTATUS0 0x1C
|
||||
#define REG_SDSTATUS1 0x1E
|
||||
|
||||
#define REG_SDIRMASK0 (0x20)
|
||||
#define REG_SDIRMASK1 (0x22)
|
||||
#define REG_SDCLKCTL (0x24)
|
||||
#define REG_SDIRMASK0 0x20
|
||||
#define REG_SDIRMASK1 0x22
|
||||
#define REG_SDCLKCTL 0x24
|
||||
|
||||
#define REG_SDBLKLEN (0x26)
|
||||
#define REG_SDOPT (0x28)
|
||||
#define REG_SDFIFO (0x30)
|
||||
#define REG_SDBLKLEN 0x26
|
||||
#define REG_SDOPT 0x28
|
||||
#define REG_SDFIFO 0x30
|
||||
|
||||
#define REG_DATACTL (0xd8)
|
||||
#define REG_SDRESET (0xe0)
|
||||
#define REG_SDPROTECTED (0xf6) //bit 0 determines if sd is protected or not?
|
||||
#define REG_DATACTL 0xD8
|
||||
#define REG_SDRESET 0xE0
|
||||
#define REG_SDPROTECTED 0xF6 //bit 0 determines if sd is protected or not?
|
||||
|
||||
#define REG_DATACTL32 (0x100)
|
||||
#define REG_SDBLKLEN32 (0x104)
|
||||
#define REG_SDBLKCOUNT32 (0x108)
|
||||
#define REG_SDFIFO32 (0x10C)
|
||||
#define REG_DATACTL32 0x100
|
||||
#define REG_SDBLKLEN32 0x104
|
||||
#define REG_SDBLKCOUNT32 0x108
|
||||
#define REG_SDFIFO32 0x10C
|
||||
|
||||
#define REG_CLK_AND_WAIT_CTL (0x138)
|
||||
#define REG_RESET_SDIO (0x1e0)
|
||||
#define REG_CLK_AND_WAIT_CTL 0x138
|
||||
#define REG_RESET_SDIO 0x1E0
|
||||
|
||||
#define TMIO_STAT0_CMDRESPEND (0x0001)
|
||||
#define TMIO_STAT0_DATAEND (0x0004)
|
||||
#define TMIO_STAT0_CARD_REMOVE (0x0008)
|
||||
#define TMIO_STAT0_CARD_INSERT (0x0010)
|
||||
#define TMIO_STAT0_SIGSTATE (0x0020)
|
||||
#define TMIO_STAT0_WRPROTECT (0x0080)
|
||||
#define TMIO_STAT0_CARD_REMOVE_A (0x0100)
|
||||
#define TMIO_STAT0_CARD_INSERT_A (0x0200)
|
||||
#define TMIO_STAT0_SIGSTATE_A (0x0400)
|
||||
#define TMIO_STAT1_CMD_IDX_ERR (0x0001)
|
||||
#define TMIO_STAT1_CRCFAIL (0x0002)
|
||||
#define TMIO_STAT1_STOPBIT_ERR (0x0004)
|
||||
#define TMIO_STAT1_DATATIMEOUT (0x0008)
|
||||
#define TMIO_STAT1_RXOVERFLOW (0x0010)
|
||||
#define TMIO_STAT1_TXUNDERRUN (0x0020)
|
||||
#define TMIO_STAT1_CMDTIMEOUT (0x0040)
|
||||
#define TMIO_STAT1_RXRDY (0x0100)
|
||||
#define TMIO_STAT1_TXRQ (0x0200)
|
||||
#define TMIO_STAT1_ILL_FUNC (0x2000)
|
||||
#define TMIO_STAT1_CMD_BUSY (0x4000)
|
||||
#define TMIO_STAT1_ILL_ACCESS (0x8000)
|
||||
#define TMIO_STAT0_CMDRESPEND 0x0001
|
||||
#define TMIO_STAT0_DATAEND 0x0004
|
||||
#define TMIO_STAT0_CARD_REMOVE 0x0008
|
||||
#define TMIO_STAT0_CARD_INSERT 0x0010
|
||||
#define TMIO_STAT0_SIGSTATE 0x0020
|
||||
#define TMIO_STAT0_WRPROTECT 0x0080
|
||||
#define TMIO_STAT0_CARD_REMOVE_A 0x0100
|
||||
#define TMIO_STAT0_CARD_INSERT_A 0x0200
|
||||
#define TMIO_STAT0_SIGSTATE_A 0x0400
|
||||
#define TMIO_STAT1_CMD_IDX_ERR 0x0001
|
||||
#define TMIO_STAT1_CRCFAIL 0x0002
|
||||
#define TMIO_STAT1_STOPBIT_ERR 0x0004
|
||||
#define TMIO_STAT1_DATATIMEOUT 0x0008
|
||||
#define TMIO_STAT1_RXOVERFLOW 0x0010
|
||||
#define TMIO_STAT1_TXUNDERRUN 0x0020
|
||||
#define TMIO_STAT1_CMDTIMEOUT 0x0040
|
||||
#define TMIO_STAT1_RXRDY 0x0100
|
||||
#define TMIO_STAT1_TXRQ 0x0200
|
||||
#define TMIO_STAT1_ILL_FUNC 0x2000
|
||||
#define TMIO_STAT1_CMD_BUSY 0x4000
|
||||
#define TMIO_STAT1_ILL_ACCESS 0x8000
|
||||
|
||||
#define TMIO_MASK_ALL (0x837F031D)
|
||||
#define TMIO_MASK_ALL 0x837F031D
|
||||
|
||||
#define TMIO_MASK_GW (TMIO_STAT1_ILL_ACCESS | TMIO_STAT1_CMDTIMEOUT | TMIO_STAT1_TXUNDERRUN | TMIO_STAT1_RXOVERFLOW | \
|
||||
TMIO_STAT1_DATATIMEOUT | TMIO_STAT1_STOPBIT_ERR | TMIO_STAT1_CRCFAIL | TMIO_STAT1_CMD_IDX_ERR)
|
||||
#define TMIO_MASK_GW (TMIO_STAT1_ILL_ACCESS | TMIO_STAT1_CMDTIMEOUT | TMIO_STAT1_TXUNDERRUN | TMIO_STAT1_RXOVERFLOW | \
|
||||
TMIO_STAT1_DATATIMEOUT | TMIO_STAT1_STOPBIT_ERR | TMIO_STAT1_CRCFAIL | TMIO_STAT1_CMD_IDX_ERR)
|
||||
|
||||
#define TMIO_MASK_READOP (TMIO_STAT1_RXRDY | TMIO_STAT1_DATAEND)
|
||||
#define TMIO_MASK_WRITEOP (TMIO_STAT1_TXRQ | TMIO_STAT1_DATAEND)
|
||||
#define TMIO_MASK_READOP (TMIO_STAT1_RXRDY | TMIO_STAT1_DATAEND)
|
||||
#define TMIO_MASK_WRITEOP (TMIO_STAT1_TXRQ | TMIO_STAT1_DATAEND)
|
||||
|
||||
#define SD_WRITE_PROTECTED (((*((vu16*)(SDMMC_BASE + REG_SDSTATUS0))) & (1 << 7 | 1 << 5)) == (1 << 5))
|
||||
typedef struct mmcdevice {
|
||||
u8 *rData;
|
||||
const u8 *tData;
|
||||
u32 size;
|
||||
u32 error;
|
||||
u16 stat0;
|
||||
u16 stat1;
|
||||
u32 ret[4];
|
||||
u32 initarg;
|
||||
u32 isSDHC;
|
||||
u32 clk;
|
||||
u32 SDOPT;
|
||||
u32 devicenumber;
|
||||
u32 total_size; //size in sectors of the device
|
||||
u32 res;
|
||||
} mmcdevice;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct mmcdevice {
|
||||
u8* rData;
|
||||
const u8* tData;
|
||||
u32 size;
|
||||
u32 error;
|
||||
u16 stat0;
|
||||
u16 stat1;
|
||||
u32 ret[4];
|
||||
u32 initarg;
|
||||
u32 isSDHC;
|
||||
u32 clk;
|
||||
u32 SDOPT;
|
||||
u32 devicenumber;
|
||||
u32 total_size; //size in sectors of the device
|
||||
u32 res;
|
||||
} mmcdevice;
|
||||
|
||||
void sdmmc_init();
|
||||
int sdmmc_sdcard_readsector(u32 sector_no, u8 *out);
|
||||
int sdmmc_sdcard_readsectors(u32 sector_no, u32 numsectors, u8 *out);
|
||||
int sdmmc_sdcard_writesector(u32 sector_no, const u8 *in);
|
||||
int sdmmc_sdcard_writesectors(u32 sector_no, u32 numsectors, const u8 *in);
|
||||
|
||||
int sdmmc_nand_readsectors(u32 sector_no, u32 numsectors, u8 *out);
|
||||
int sdmmc_nand_writesectors(u32 sector_no, u32 numsectors, const u8 *in);
|
||||
|
||||
int sdmmc_get_cid(bool isNand, u32 *info);
|
||||
|
||||
mmcdevice *getMMCDevice(int drive);
|
||||
|
||||
int Nand_Init();
|
||||
int SD_Init();
|
||||
u32 sdmmc_sdcard_init();
|
||||
|
||||
#ifdef __cplusplus
|
||||
};
|
||||
#endif
|
||||
|
||||
//---------------------------------------------------------------------------------
|
||||
static inline u16 sdmmc_read16(u16 reg) {
|
||||
//---------------------------------------------------------------------------------
|
||||
return *(volatile u16*)(SDMMC_BASE + reg);
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------
|
||||
static inline void sdmmc_write16(u16 reg, u16 val) {
|
||||
//---------------------------------------------------------------------------------
|
||||
*(volatile u16*)(SDMMC_BASE + reg) = val;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------
|
||||
static inline u32 sdmmc_read32(u16 reg) {
|
||||
//---------------------------------------------------------------------------------
|
||||
return *(volatile u32*)(SDMMC_BASE + reg);
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------
|
||||
static inline void sdmmc_write32(u16 reg, u32 val) {
|
||||
//---------------------------------------------------------------------------------
|
||||
*(volatile u32*)(SDMMC_BASE + reg) = val;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------
|
||||
static inline void sdmmc_mask16(u16 reg, const u16 clear, const u16 set) {
|
||||
//---------------------------------------------------------------------------------
|
||||
u16 val = sdmmc_read16(reg);
|
||||
val &= ~clear;
|
||||
val |= set;
|
||||
sdmmc_write16(reg, val);
|
||||
}
|
||||
|
||||
static inline void setckl(u32 data)
|
||||
{
|
||||
sdmmc_write16(REG_SDCLKCTL, data & 0xFF);
|
||||
sdmmc_write16(REG_SDCLKCTL, 1u<<8 | (data & 0x2FF));
|
||||
}
|
||||
u32 sdmmc_sdcard_init();
|
||||
int sdmmc_sdcard_readsectors(u32 sector_no, u32 numsectors, u8 *out);
|
||||
int sdmmc_sdcard_writesectors(u32 sector_no, u32 numsectors, const u8 *in);
|
||||
int sdmmc_nand_readsectors(u32 sector_no, u32 numsectors, u8 *out);
|
||||
int sdmmc_nand_writesectors(u32 sector_no, u32 numsectors, const u8 *in);
|
||||
void sdmmc_get_cid(bool isNand, u32 *info);
|
||||
mmcdevice *getMMCDevice(int drive);
|
||||
@ -1,11 +0,0 @@
|
||||
.arm
|
||||
|
||||
.section .text.wait_cycles, "ax", %progbits
|
||||
.align 2
|
||||
.global wait_cycles
|
||||
.type wait_cycles, %function
|
||||
wait_cycles:
|
||||
subs r0, #2
|
||||
nop
|
||||
bgt wait_cycles
|
||||
bx lr
|
||||
Reference in New Issue
Block a user