Fix indentation
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29d8e637d8
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@ -27,13 +27,13 @@ start:
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Set MPU permissions and cache settings
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@ Set MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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ldr r1, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r1, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r2, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r2, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r3, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r3, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r4, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r4, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r5, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r5, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r6, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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ldr r6, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r7, #0
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mov r7, #0
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mov r8, #0x15
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mov r8, #0x15
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r0, c6, c0, 0
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@ -44,9 +44,9 @@ start:
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 4
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 4
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@ Enable caches / MPU
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@ Enable caches / MPU
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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