kext: fix outer memory cacheability on newer versions
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@ -114,6 +114,8 @@ u32 installK11Extension(u8 *pos, u32 size, bool needToInitSd, u32 baseK11VA, u32
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void *originalHandlers[4];
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u32 L1MMUTableAddrs[4];
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volatile bool done;
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struct CfwInfo
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{
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char magic[4];
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@ -181,6 +183,7 @@ u32 installK11Extension(u8 *pos, u32 size, bool needToInitSd, u32 baseK11VA, u32
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struct KExtParameters *p = (struct KExtParameters *)(*(u32 *)0x18000024 - K11EXT_VA + 0x18000000);
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p->basePA = dstKextPA;
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p->done = false;
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p->stolenSystemMemRegionSize = stolenSystemMemRegionSize;
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for(u32 i = 0; i < 4; i++)
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@ -41,6 +41,8 @@ struct KExtParameters
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void *originalHandlers[4];
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u32 L1MMUTableAddrs[4];
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volatile bool done;
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CfwInfo cfwInfo;
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} kExtParameters = { .basePA = 0x12345678 }; // place this in .data
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@ -60,15 +62,31 @@ void relocateAndSetupMMU(u32 coreId, u32 *L1Table)
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memset((u32 *)(p0->basePA + (__bss_start__ - __start__)), 0, __bss_end__ - __bss_start__);
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// Map the kernel ext at K11EXT_VA
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// 4KB extended small pages: [SYS:RW USR:-- X TYP:NORMAL SHARED OUTER NOCACHE, INNER CACHED WB WA]
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// 4KB extended small pages:
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// Outer Write-Through cached, No Allocate on Write, Buffered
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// Inner Cached Write-Back Write-Allocate, Buffered
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// This was changed at some point (8.0 maybe?), it was outer noncached before
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for(u32 offset = 0; offset < (u32)(__end__ - __start__); offset += 0x1000)
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L2Table[offset >> 12] = (p0->basePA + offset) | 0x516;
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L2Table[offset >> 12] = (p0->basePA + offset) | 0x596;
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p0->done = true;
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// DSB, Flush Prefetch Buffer (more or less "isb")
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__asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" :: "r" (0) : "memory");
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__asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
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__asm__ __volatile__ ("sev");
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}
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else
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else {
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do
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{
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__asm__ __volatile__ ("wfe");
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} while(!p0->done);
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// DSB, Flush Prefetch Buffer (more or less "isb")
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__asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" :: "r" (0) : "memory");
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__asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
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}
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// bit31 idea thanks to SALT
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// Maps physmem so that, if addr is in physmem(0, 0x30000000), it can be accessed uncached&rwx as addr|(1<<31)
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u32 attribs = 0x40C02; // supersection (rwx for all) of strongly ordered memory, shared
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@ -82,6 +100,10 @@ void relocateAndSetupMMU(u32 coreId, u32 *L1Table)
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L1Table[K11EXT_VA >> 20] = (u32)L2Table | 1;
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p->L1MMUTableAddrs[coreId] = (u32)L1Table;
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// DSB, Flush Prefetch Buffer (more or less "isb")
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__asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" :: "r" (0) : "memory");
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__asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
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}
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void bindSGI0Hook(void)
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