diff --git a/arm9/source/patches.c b/arm9/source/patches.c
index f441eb3..d00e3c9 100644
--- a/arm9/source/patches.c
+++ b/arm9/source/patches.c
@@ -114,6 +114,8 @@ u32 installK11Extension(u8 *pos, u32 size, bool needToInitSd, u32 baseK11VA, u32
         void *originalHandlers[4];
         u32 L1MMUTableAddrs[4];
 
+        volatile bool done;
+
         struct CfwInfo
         {
             char magic[4];
@@ -181,6 +183,7 @@ u32 installK11Extension(u8 *pos, u32 size, bool needToInitSd, u32 baseK11VA, u32
 
     struct KExtParameters *p = (struct KExtParameters *)(*(u32 *)0x18000024 - K11EXT_VA + 0x18000000);
     p->basePA = dstKextPA;
+    p->done = false;
     p->stolenSystemMemRegionSize = stolenSystemMemRegionSize;
 
     for(u32 i = 0; i < 4; i++)
diff --git a/k11_extension/source/main.c b/k11_extension/source/main.c
index 4250f3f..d6f466f 100644
--- a/k11_extension/source/main.c
+++ b/k11_extension/source/main.c
@@ -41,6 +41,8 @@ struct KExtParameters
     void *originalHandlers[4];
     u32 L1MMUTableAddrs[4];
 
+    volatile bool done;
+
     CfwInfo cfwInfo;
 } kExtParameters = { .basePA = 0x12345678 }; // place this in .data
 
@@ -60,15 +62,31 @@ void relocateAndSetupMMU(u32 coreId, u32 *L1Table)
         memset((u32 *)(p0->basePA + (__bss_start__ - __start__)), 0, __bss_end__ - __bss_start__);
 
         // Map the kernel ext at K11EXT_VA
-        // 4KB extended small pages: [SYS:RW USR:-- X  TYP:NORMAL SHARED OUTER NOCACHE, INNER CACHED WB WA]
+        // 4KB extended small pages:
+        // Outer Write-Through cached, No Allocate on Write, Buffered
+        // Inner Cached Write-Back Write-Allocate, Buffered
+        // This was changed at some point (8.0 maybe?), it was outer noncached before
         for(u32 offset = 0; offset < (u32)(__end__ - __start__); offset += 0x1000)
-            L2Table[offset >> 12] = (p0->basePA + offset) | 0x516;
+            L2Table[offset >> 12] = (p0->basePA + offset) | 0x596;
+
+        p0->done = true;
+
+        // DSB, Flush Prefetch Buffer (more or less "isb")
+        __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" :: "r" (0) : "memory");
+        __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
 
         __asm__ __volatile__ ("sev");
     }
-    else
-        __asm__ __volatile__ ("wfe");
+    else {
+        do
+        {
+            __asm__ __volatile__ ("wfe");
+        } while(!p0->done);
 
+        // DSB, Flush Prefetch Buffer (more or less "isb")
+        __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" :: "r" (0) : "memory");
+        __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
+    }
     // bit31 idea thanks to SALT
     // Maps physmem so that, if addr is in physmem(0, 0x30000000), it can be accessed uncached&rwx as addr|(1<<31)
     u32 attribs = 0x40C02; // supersection (rwx for all) of strongly ordered memory, shared
@@ -82,6 +100,10 @@ void relocateAndSetupMMU(u32 coreId, u32 *L1Table)
     L1Table[K11EXT_VA >> 20] = (u32)L2Table | 1;
 
     p->L1MMUTableAddrs[coreId] = (u32)L1Table;
+
+    // DSB, Flush Prefetch Buffer (more or less "isb")
+    __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" :: "r" (0) : "memory");
+    __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory");
 }
 
 void bindSGI0Hook(void)