LowLevel/Luma3DS-3GX
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Cleanup

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This commit is contained in:
Aurora
2016-07-01 20:27:28 +02:00
parent 61684ecb68
commit 136e0d8974
14 changed files with 151 additions and 156 deletions
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4
source/cache.s
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@@ -47,7 +47,7 @@ flushDCacheRange:
mcr p15, 0, r0, c7, c14, 1 @ clean and flush the line corresponding to the address r0 is holding
add r0, #0x20
cmp r0, r1
blt flush_dcache_range_loop
blo flush_dcache_range_loop
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
@@ -74,7 +74,7 @@ flushICacheRange:
mcr p15, 0, r0, c7, c5, 1 @ flush the line corresponding to the address r0 is holding
add r0, #0x20
cmp r0, r1
blt flush_icache_range_loop
blo flush_icache_range_loop
bx lr

8
source/config.c
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@@ -145,6 +145,9 @@ void configureCFW(const char *configPath)
u32 oldEnabled = multiOptions[selectedOption].enabled;
drawCharacter(selected, 10 + multiOptions[selectedOption].posXs[oldEnabled] * SPACING_X, multiOptions[selectedOption].posY, COLOR_BLACK);
multiOptions[selectedOption].enabled = oldEnabled == 3 ? 0 : oldEnabled + 1;
if(!selectedOption)
updateBrightness(multiOptions[selectedOption].enabled);
}
else
{
@@ -156,12 +159,7 @@ void configureCFW(const char *configPath)
//In any case, if the current option is enabled (or a multiple choice option is selected) we must display a red 'x'
if(selectedOption < multiOptionsAmount)
{
if(selectedOption == 0)
updateBrightness(multiOptions[selectedOption].enabled);
drawCharacter(selected, 10 + multiOptions[selectedOption].posXs[multiOptions[selectedOption].enabled] * SPACING_X, multiOptions[selectedOption].posY, COLOR_RED);
}
else
{
u32 singleSelected = selectedOption - multiOptionsAmount;

2
source/draw.h
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@@ -19,6 +19,8 @@
#define COLOR_RED 0x0000FF
#define COLOR_BLACK 0x000000
extern volatile struct fb *const fb;
u32 loadSplash(void);
void drawCharacter(char character, int posX, int posY, u32 color);
int drawString(const char *string, int posX, int posY, u32 color);

6
source/firm.c
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@@ -22,7 +22,7 @@ static const firmSectionHeader *section;
u32 config,
isN3DS,
emuOffset;
FirmwareSource firmSource;
void main(void)
@@ -37,7 +37,7 @@ void main(void)
FirmwareSource nandType;
ConfigurationStatus needConfig;
A9LHMode a9lhMode;
//Detect the console being used
isN3DS = PDN_MPCORE_CFG == 7;
@@ -381,7 +381,7 @@ static inline void launchFirm(FirmwareType firmType, u32 isFirmlaunch)
flushEntireDCache(); //Ensure that all memory transfers have completed and that the data cache has been flushed
flushEntireICache();
//Set ARM11 kernel entrypoint
*arm11 = (u32)firm->arm11Entry;

61
source/screen.c
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@@ -12,18 +12,17 @@
#include "draw.h"
#include "i2c.h"
#define ARM11_STUB_ADDRESS (0x25000000 - 0x40) //It's currently only 0x28 bytes large. We're putting 0x40 just to be sure here
#define WAIT_FOR_ARM9() *arm11Entry = 0; while(!*arm11Entry); ((void (*)())*arm11Entry)();
vu32 *arm11Entry = (vu32 *)0x1FFFFFF8;
volatile struct fb *const fb = (volatile struct fb *)0x23FFFE00;
void __attribute__((naked)) arm11Stub(void)
{
//Disable interrupts
__asm(".word 0xF10C01C0");
//Wait for the entry to be set
while(*arm11Entry == ARM11_STUB_ADDRESS);
//Jump to it
((void (*)())*arm11Entry)();
}
@@ -31,12 +30,14 @@ void __attribute__((naked)) arm11Stub(void)
static inline void invokeArm11Function(void (*func)())
{
static u32 hasCopiedStub = 0;
if(!hasCopiedStub++)
if(!hasCopiedStub)
{
memcpy((void *)ARM11_STUB_ADDRESS, arm11Stub, 0x40);
flushDCacheRange((void *)ARM11_STUB_ADDRESS, 0x40);
hasCopiedStub = 1;
}
*arm11Entry = (u32)func;
while(*arm11Entry);
*arm11Entry = ARM11_STUB_ADDRESS;
@@ -62,25 +63,23 @@ void deinitScreens(void)
if(PDN_GPU_CNT != 1) invokeArm11Function(ARM11);
}
void updateBrightness(u32 brightnessLevel)
void updateBrightness(u32 brightnessIndex)
{
static int brightnessValue;
brightnessValue = brightness[brightnessLevel];
u32 brightnessLevel = brightness[brightnessIndex];
void __attribute__((naked)) ARM11(void)
{
//Disable interrupts
__asm(".word 0xF10C01C0");
__asm(".word 0xF10C01C0");
//Change brightness
*(vu32 *)0x10202240 = brightnessValue;
*(vu32 *)0x10202A40 = brightnessValue;
*(vu32 *)0x10202240 = brightnessLevel;
*(vu32 *)0x10202A40 = brightnessLevel;
WAIT_FOR_ARM9();
}
flushDCacheRange(&brightnessValue, 4);
flushDCacheRange(&brightnessLevel, 4);
invokeArm11Function(ARM11);
}
@@ -90,21 +89,20 @@ void clearScreens(void)
{
//Disable interrupts
__asm(".word 0xF10C01C0");
//Setting up two simultaneous memory fills using the GPU
vu32 *REGs_PSC0 = (vu32 *)0x10400010;
REGs_PSC0[0] = (u32)fb->top_left >> 3; //Start address
REGs_PSC0[1] = (u32)(fb->top_left + 0x46500) >> 3; //End address
REGs_PSC0[2] = 0; //Fill value
REGs_PSC0[3] = (2 << 8) | 1; //32-bit patter; start
REGs_PSC0[3] = (2 << 8) | 1; //32-bit pattern; start
vu32 *REGs_PSC1 = (vu32 *)0x10400020;
REGs_PSC1[0] = (u32)fb->bottom >> 3; //Start address
REGs_PSC1[1] = (u32)(fb->bottom + 0x38400) >> 3; //End address
REGs_PSC1[2] = 0; //Fill value
REGs_PSC1[3] = (2 << 8) | 1; //32-bit patter; start
REGs_PSC1[3] = (2 << 8) | 1; //32-bit pattern; start
while(!((REGs_PSC0[3] & 2) && (REGs_PSC1[3] & 2)));
if(fb->top_right != fb->top_left)
@@ -112,14 +110,14 @@ void clearScreens(void)
REGs_PSC0[0] = (u32)fb->top_right >> 3; //Start address
REGs_PSC0[1] = (u32)(fb->top_right + 0x46500) >> 3; //End address
REGs_PSC0[2] = 0; //Fill value
REGs_PSC0[3] = (2 << 8) | 1; //32-bit patter; start
REGs_PSC0[3] = (2 << 8) | 1; //32-bit pattern; start
while(!(REGs_PSC0[3] & 2));
}
WAIT_FOR_ARM9();
}
flushDCacheRange((void *)fb, sizeof(struct fb));
invokeArm11Function(ARM11);
}
@@ -133,13 +131,13 @@ u32 initScreens(void)
//Disable interrupts
__asm(".word 0xF10C01C0");
u32 brightnessLevel = MULTICONFIG(0);
u32 brightnessLevel = brightness[MULTICONFIG(0)];
*(vu32 *)0x10141200 = 0x1007F;
*(vu32 *)0x10202014 = 0x00000001;
*(vu32 *)0x1020200C &= 0xFFFEFFFE;
*(vu32 *)0x10202240 = brightness[brightnessLevel];
*(vu32 *)0x10202A40 = brightness[brightnessLevel];
*(vu32 *)0x10202240 = brightnessLevel;
*(vu32 *)0x10202A40 = brightnessLevel;
*(vu32 *)0x10202244 = 0x1023E;
*(vu32 *)0x10202A44 = 0x1023E;
@@ -225,7 +223,7 @@ u32 initScreens(void)
WAIT_FOR_ARM9();
}
if(needToInit)
{
flushDCacheRange(&config, 4);
@@ -235,9 +233,8 @@ u32 initScreens(void)
//Turn on backlight
i2cWriteRegister(I2C_DEV_MCU, 0x22, 0x2A);
}
else
updateBrightness(MULTICONFIG(0));
else updateBrightness(MULTICONFIG(0));
clearScreens();
return needToInit;

8
source/screen.h
View File

@@ -10,14 +10,16 @@
#include "types.h"
#define PDN_GPU_CNT (*(vu8 *)0x10141200)
#define ARM11_STUB_ADDRESS (0x25000000 - 0x40) //It's currently only 0x28 bytes large. We're putting 0x40 just to be sure here
#define WAIT_FOR_ARM9() *arm11Entry = 0; while(!*arm11Entry); ((void (*)())*arm11Entry)();
static volatile struct fb {
struct fb {
u8 *top_left;
u8 *top_right;
u8 *bottom;
} *const fb = (volatile struct fb *)0x23FFFE00;
};
void deinitScreens(void);
void updateBrightness(u32 brightnessLevel);
void updateBrightness(u32 brightnessIndex);
void clearScreens(void);
u32 initScreens(void);

52
source/start.s
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@@ -10,28 +10,32 @@ start:
@ Change the stack pointer
mov sp, #0x27000000
@ Disable caches / mpu
@ Disable caches / MPU
mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, #(1<<12) @ - instruction cache disable
bic r0, #(1<<2) @ - data cache disable
bic r0, #(1<<0) @ - mpu disable
mcr p15, 0, r0, c1, c0, 0 @ write control register
@ Flush caches
bl flushEntireDCache
bl flushEntireICache
@ Give read/write access to all the memory regions
ldr r0, =0x33333333
ldr r0, =0x3333333
mcr p15, 0, r0, c5, c0, 2 @ write data access
mcr p15, 0, r0, c5, c0, 3 @ write instruction access
@ Sets MPU permissions and cache settings
ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
ldr r1, =0x3000801B @ fff00000 16k | dtcm
ldr r2, =0x01FF801D @ 01ff8000 32k | itcm
ldr r3, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
ldr r4, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
mov r8, #0x29
@ Set MPU permissions and cache settings
ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
ldr r1, =0x01FF801D @ 01ff8000 32k | itcm
ldr r2, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
ldr r3, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
ldr r4, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
ldr r5, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
ldr r6, =0x1800002D @ 18000000 8M | vram (+ 2MB)
mov r7, #0
mov r8, #0x15
mcr p15, 0, r0, c6, c0, 0
mcr p15, 0, r1, c6, c1, 0
mcr p15, 0, r2, c6, c2, 0
@@ -40,30 +44,18 @@ start:
mcr p15, 0, r5, c6, c5, 0
mcr p15, 0, r6, c6, c6, 0
mcr p15, 0, r7, c6, c7, 0
mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 3, 5
mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 3, 5
mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 3, 5
mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 4
mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 4
mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 4
@ Enable dctm
ldr r0, =0x3000800A @ set dtcm
mcr p15, 0, r0, c9, c1, 0 @ set the dtcm Region Register
@ Enable caches
@ Enable caches / MPU
mrc p15, 0, r0, c1, c0, 0 @ read control register
orr r0, r0, #(1<<18) @ - itcm enable
orr r0, r0, #(1<<16) @ - dtcm enable
orr r0, r0, #(1<<12) @ - instruction cache enable
orr r0, r0, #(1<<2) @ - data cache enable
orr r0, r0, #(1<<0) @ - mpu enable
mcr p15, 0, r0, c1, c0, 0 @ write control register
@ Flush caches
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
mcr p15, 0, r0, c7, c6, 0 @ flush D-cache
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
@ Fixes mounting of SDMC
@ Fix mounting of SDMC
ldr r0, =0x10000020
mov r1, #0x340
str r1, [r0]

2
source/utils.c
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@@ -38,7 +38,7 @@ u32 waitInput(void)
void mcuReboot(void)
{
flushEntireDCache(); //Ensure that all memory transfers have completed and that the data cache has been flushed
i2cWriteRegister(I2C_DEV_MCU, 0x20, 1 << 2);
while(1);
}