80 lines
2.4 KiB
ArmAsm
80 lines
2.4 KiB
ArmAsm
@
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@ cache.s
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@ by TuxSH
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@
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@ This is part of Luma3DS, see LICENSE.txt for details
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@
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.text
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.arm
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.align 4
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.global flushEntireDCache
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.type flushEntireDCache, %function
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flushEntireDCache:
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@ Adpated from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0155a/ch03s03s05.html ,
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@ and https://github.com/gemarcano/libctr9_io/blob/master/src/ctr_system_ARM.c#L39 as well
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@ Note: ARM's example is actually for a 8KB DCache (which is what the 3DS has)
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@ Implemented in bootROM at address 0xffff0830
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mov r1, #0 @ segment counter
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outer_loop:
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mov r0, #0 @ line counter
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inner_loop:
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orr r2, r1, r0 @ generate segment and line address
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mcr p15, 0, r2, c7, c14, 2 @ clean and flush the line
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add r0, #0x20 @ increment to next line
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cmp r0, #0x400
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bne inner_loop
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add r1, #0x40000000
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cmp r1, #0
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bne outer_loop
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mcr p15, 0, r1, c7, c10, 4 @ drain write buffer
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bx lr
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.global flushDCacheRange
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.type flushDCacheRange, %function
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flushDCacheRange:
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@ Implemented in bootROM at address 0xffff08a0
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add r1, r0, r1 @ end address
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bic r0, #0x1f @ align source address to cache line size (32 bytes)
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flush_dcache_range_loop:
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mcr p15, 0, r0, c7, c14, 1 @ clean and flush the line corresponding to the address r0 is holding
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add r0, #0x20
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cmp r0, r1
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blo flush_dcache_range_loop
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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bx lr
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.global flushEntireICache
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.type flushEntireICache, %function
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flushEntireICache:
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@ Implemented in bootROM at address 0xffff0ab4
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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bx lr
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.global flushICacheRange
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.type flushICacheRange, %function
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flushICacheRange:
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@ Implemented in bootROM at address 0xffff0ac0
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add r1, r0, r1 @ end address
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bic r0, #0x1f @ align source address to cache line size (32 bytes)
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flush_icache_range_loop:
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mcr p15, 0, r0, c7, c5, 1 @ flush the line corresponding to the address r0 is holding
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add r0, #0x20
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cmp r0, r1
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blo flush_icache_range_loop
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bx lr
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