102 lines
3.4 KiB
ArmAsm
102 lines
3.4 KiB
ArmAsm
@ This file is part of Luma3DS
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@ Copyright (C) 2016 Aurora Wright, TuxSH
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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@
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@ Additional Terms 7.b of GPLv3 applies to this file: Requiring preservation of specified
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@ reasonable legal notices or author attributions in that material or in the Appropriate Legal
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@ Notices displayed by works containing it.
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@ Thanks to the numerous people who took part in writing this file
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.section .text.start
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.align 4
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.global _start
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_start:
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b start
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.global launchedFirmTidLow
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launchedFirmTidLow:
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.hword 0, 0, 0, 0, 0, 0, 0, 0
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start:
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@ Disable interrupts
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mrs r0, cpsr
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orr r0, #0x1C0
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msr cpsr_cx, r0
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@ Change the stack pointer
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mov sp, #0x27000000
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@ Disable caches / MPU
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, #(1<<12) @ - instruction cache disable
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bic r0, #(1<<2) @ - data cache disable
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bic r0, #(1<<0) @ - mpu disable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Flush caches
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bl flushEntireDCache
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bl flushEntireICache
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@ Give read/write access to all the memory regions
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ldr r0, =0x3333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Set MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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ldr r1, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r2, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r3, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r4, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r5, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r6, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r7, #0
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mov r8, #0x15
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 4
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 4
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@ Enable caches / MPU / ITCM
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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orr r0, r0, #(1<<18) @ - ITCM enable
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orr r0, r0, #(1<<13) @ - alternate exception vectors enable
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orr r0, r0, #(1<<12) @ - instruction cache enable
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orr r0, r0, #(1<<2) @ - data cache enable
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orr r0, r0, #(1<<0) @ - mpu enable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Fix mounting of SDMC
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ldr r0, =0x10000020
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mov r1, #0x340
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str r1, [r0]
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@ Clear BSS
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ldr r0, =__bss_start
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mov r1, #0
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ldr r2, =__bss_end
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sub r2, r0
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bl memset32
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b main
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