58 lines
1.6 KiB
ArmAsm
58 lines
1.6 KiB
ArmAsm
@
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@ handlers.s
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@ by TuxSH
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@
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@ This is part of Luma3DS, see LICENSE.txt for details
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@
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.macro GEN_HANDLER name
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.global \name
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.type \name, %function
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\name:
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ldr sp, =#0x02000000 @ We make the (full descending) stack point to the end of ITCM for our exception handlers.
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@ It doesn't matter if we're overwriting stuff here, since we're going to reboot.
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stmfd sp!, {r0-r7} @ FIQ has its own r8-r14 regs
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ldr r1, =\@ @ macro expansion counter
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b _commonHandler
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.size \name, . - \name
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.endm
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.text
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.arm
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.align 4
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.global _commonHandler
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.type _commonHandler, %function
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_commonHandler:
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mrs r2, spsr
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mov r6, sp
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mrs r3, cpsr
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orr r3, #0x1c0 @ disable Imprecise Aborts, IRQ and FIQ (AIF)
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ands r4, r2, #0xf @ get the mode that triggered the exception
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moveq r4, #0xf @ usr => sys
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bic r5, r3, #0xf
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orr r5, r4
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msr cpsr_c, r5 @ change processor mode
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stmfd r6!, {r8-lr}
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msr cpsr_c, r3 @ restore processor mode
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mov sp, r6
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stmfd sp!, {r2,lr}
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mrc p15,0,r3,c5,c0,0 @ dfsr
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mrc p15,0,r4,c5,c0,1 @ ifsr
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mrc p15,0,r5,c6,c0,0 @ far
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stmfd sp!, {r3-r5} @ it's a bit of a mess, but we will fix that later
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@ order of saved regs now: dfsr, ifsr, far, cpsr, pc + (2/4/8), r8-r14, r0-r7
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mov r0, sp
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b mainHandler
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GEN_HANDLER FIQHandler
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GEN_HANDLER undefinedInstructionHandler
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GEN_HANDLER prefetchAbortHandler
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GEN_HANDLER dataAbortHandler
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