250 lines
6.1 KiB
ArmAsm
250 lines
6.1 KiB
ArmAsm
@ This file is part of Luma3DS
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@ Copyright (C) 2016-2017 Aurora Wright, TuxSH
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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@
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@ Additional Terms 7.b and 7.c of GPLv3 apply to this file:
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@ * Requiring preservation of specified reasonable legal notices or
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@ author attributions in that material or in the Appropriate Legal
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@ Notices displayed by works containing it.
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@ * Prohibiting misrepresentation of the origin of that material,
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@ or requiring that modified versions of such material be marked in
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@ reasonable ways as different from the original version.
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.macro TEST_IF_MODE_AND_ARM_INST_OR_JUMP lbl, mode
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cpsid aif
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mrs sp, spsr
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tst sp, #0x20
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bne \lbl
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and sp, #0x1f @ get previous processor mode
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cmp sp, #\mode
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bne \lbl
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sub sp, lr, #4
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mcr p15, 0, sp, c7, c8, 0 @ VA to PA translation with privileged read permission check
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mrc p15, 0, sp, c7, c4, 0 @ read PA register
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tst sp, #1 @ failure bit
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bne \lbl
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.endm
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.macro GEN_USUAL_HANDLER name, index, pos
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\name\()Handler:
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ldr sp, =exceptionStackTop
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ldr sp, [sp]
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sub sp, #0x100
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push {r0-r12, lr}
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mrs r0, spsr
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bl isExceptionFatal
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cmp r0, #0
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pop {r0-r12, lr}
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bne _exc_is_fatal_\name
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ldr sp, =originalHandlers
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ldr sp, [sp, #\pos]
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bx sp
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_exc_is_fatal_\name:
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push {r8, r9}
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mov r8, #\index
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b _commonHandler
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.endm
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.text
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.arm
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.balign 4
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_die:
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cpsid aif
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_die_loop:
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wfi
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b _die_loop
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_commonHandler:
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cpsid aif
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push {r0}
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ldr r0, =_fatalExceptionOccured
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ldr r0, [r0]
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cmp r0, #0
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bne _die_loop
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pop {r0}
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ldr r9, =_regs
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stmia r9, {r0-r7}
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mov r1, r8
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pop {r8,r9}
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ldr r0, =_fatalExceptionOccured
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mov r4, #1
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_try_lock:
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ldrex r2, [r0]
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strex r3, r4, [r0]
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cmp r3, #0
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bne _try_lock
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push {r1, r12, lr} @ attempt to hang the other cores
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adr r0, _die
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mov r1, #0xf
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mov r2, #1
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mov r3, #0
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bl executeFunctionOnCores
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pop {r1, r12, lr}
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mrs r2, spsr
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mrs r3, cpsr
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ldr r6, =_regs
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add r6, #0x20
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ands r4, r2, #0xf @ get the mode that triggered the exception
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moveq r4, #0xf @ usr => sys
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bic r5, r3, #0xf
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orr r5, r4
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msr cpsr_c, r5 @ change processor mode
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stmia r6!, {r8-lr}
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msr cpsr_c, r3 @ restore processor mode
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str lr, [r6], #4
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str r2, [r6], #4
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mov r0, r6
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mrc p15, 0, r4, c5, c0, 0 @ dfsr
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mrc p15, 0, r5, c5, c0, 1 @ ifsr
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mrc p15, 0, r6, c6, c0, 0 @ far
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fmrx r7, fpexc
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fmrx r8, fpinst
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fmrx r9, fpinst2
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bic r3, #(1<<31)
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fmxr fpexc, r3 @ clear the VFP11 exception flag (if it's set)
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stmia r0!, {r4-r9}
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mov r0, #0
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mcr p15, 0, r0, c7, c14, 0 @ Clean and Invalidate Entire Data Cache
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mcr p15, 0, r0, c7, c10, 4 @ Drain Synchronization Barrier
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ldr r0, =isN3DS
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ldrb r0, [r0]
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cmp r0, #0
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beq _no_L2C
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ldr r0, =(0x17e10100 | 1 << 31)
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ldr r0, [r0]
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tst r0, #1 @ is the L2C enabled?
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beq _no_L2C
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ldr r0, =0xffff
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ldr r2, =(0x17e10730 | 1 << 31)
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str r0, [r2, #0x4c] @ invalidate by way
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_L2C_sync:
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ldr r0, [r2] @ L2C cache sync register
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tst r0, #1
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bne _L2C_sync
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_no_L2C:
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cps #0x1F
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ldr sp, =exceptionStackTop
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ldr sp, [sp]
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sub sp, #0x100
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 5 @ Drain Memory Barrier
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ldr r0, =_regs
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mrc p15, 0, r2, c0, c0, 5 @ CPU ID register
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bl fatalExceptionHandlersMain
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ldr r12, =mcuReboot
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ldr r12, [r12]
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bx r12
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.global FIQHandler
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.type FIQHandler, %function
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GEN_USUAL_HANDLER FIQ, 0, 28
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.global undefinedInstructionHandler
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.type undefinedInstructionHandler, %function
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undefinedInstructionHandler:
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TEST_IF_MODE_AND_ARM_INST_OR_JUMP _undefinedInstructionNormalHandler, 0x10
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ldr sp, [lr, #-4] @ test if it's an VFP instruction that was aborted
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lsl sp, #4
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sub sp, #0xc0000000
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cmp sp, #0x30000000
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bcs _undefinedInstructionNormalHandler
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fmrx sp, fpexc
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tst sp, #0x40000000
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bne _undefinedInstructionNormalHandler
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@ FPU init
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sub lr, #4
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srsfd sp!, #0x13
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cps #0x13
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stmfd sp, {r0-r3, r11-lr}^
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sub sp, #0x20
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ldr r12, =initFPU
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ldr r12, [r12]
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blx r12
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ldmfd sp, {r0-r3, r11-lr}^
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add sp, #0x20
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rfefd sp! @ retry aborted instruction
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GEN_USUAL_HANDLER _undefinedInstructionNormal, 1, 4
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.global prefetchAbortHandler
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.type prefetchAbortHandler, %function
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prefetchAbortHandler:
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TEST_IF_MODE_AND_ARM_INST_OR_JUMP _prefetchAbortNormalHandler, 0x13
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ldr sp, =(Break + 3*4 + 4)
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cmp lr, sp
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bne _prefetchAbortNormalHandler
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sub sp, r0, #0x110
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pop {r0-r7, r12, lr}
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pop {r8-r11}
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ldr lr, [sp, #8]!
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ldr sp, [sp, #4]
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msr spsr, sp
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addne lr, #2 @ adjust address for later
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GEN_USUAL_HANDLER _prefetchAbortNormal, 2, 12
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.global dataAbortHandler
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.type dataAbortHandler, %function
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dataAbortHandler:
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ldr sp, =exceptionStackTop
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ldr sp, [sp]
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push {r0-r12, lr}
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mrs r0, spsr
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sub r1, lr, #8
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bl isDataAbortExceptionRangeControlled
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cmp r0, #0
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pop {r0-r12, lr}
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beq _dataAbortNormalHandler
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msr spsr_f, #(1 << 30)
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mov r12, #0
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subs pc, lr, #4
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GEN_USUAL_HANDLER _dataAbortNormal, 3, 16
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.bss
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.balign 4
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_regs: .skip (4 * 23)
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_fatalExceptionOccured: .word 0
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