21db0d45bd
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114 lines
3.8 KiB
ArmAsm
114 lines
3.8 KiB
ArmAsm
@ This file is part of Luma3DS
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@ Copyright (C) 2016-2017 Aurora Wright, TuxSH
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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@
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@ Additional Terms 7.b and 7.c of GPLv3 apply to this file:
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@ * Requiring preservation of specified reasonable legal notices or
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@ author attributions in that material or in the Appropriate Legal
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@ Notices displayed by works containing it.
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@ * Prohibiting misrepresentation of the origin of that material,
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@ or requiring that modified versions of such material be marked in
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@ reasonable ways as different from the original version.
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.macro GEN_HANDLER name
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.global \name
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.type \name, %function
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\name:
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ldr sp, =#0x02000000 @ We make the (full descending) stack point to the end of ITCM for our exception handlers.
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@ It doesn't matter if we're overwriting stuff here, since we're going to reboot.
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stmfd sp!, {r0-r7} @ FIQ has its own r8-r14 regs
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ldr r1, =\@ @ macro expansion counter
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b _commonHandler
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.size \name, . - \name
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.endm
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.text
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.arm
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.align 4
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.global _commonHandler
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.type _commonHandler, %function
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_commonHandler:
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mrs r2, spsr
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mov r6, sp
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mrs r3, cpsr
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orr r3, #0x1c0 @ disable Imprecise Aborts, IRQ and FIQ (equivalent to "cpsid aif" on arm11)
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msr cpsr_cx, r3
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tst r2, #0x20
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bne noSvcBreak
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cmp r1, #2
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bne noSvcBreak
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sub r0, lr, #4 @ calling cannotAccessAddress cause more problems that it actually solves... (I've to save a lot of regs and that's a pain tbh)
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lsr r0, #20 @ we'll just do some address checks (to see if it's in ARM9 internal memory)
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cmp r0, #0x80
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bne noSvcBreak
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ldr r4, [lr, #-4]
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ldr r5, =#0xe12fff7f
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cmp r4, r5
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bne noSvcBreak
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bic r5, r3, #0xf
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orr r5, #0x3
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msr cpsr_c, r5 @ switch to supervisor mode
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ldmfd sp, {r8-r11}^
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ldr r2, [sp, #0x1c] @ implementation details of the official svc handler
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ldr r4, [sp, #0x18]
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msr cpsr_c, r3 @ restore processor mode
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tst r2, #0x20
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addne lr, r4, #2 @ adjust address for later
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moveq lr, r4
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noSvcBreak:
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ands r4, r2, #0xf @ get the mode that triggered the exception
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moveq r4, #0xf @ usr => sys
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bic r5, r3, #0xf
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orr r5, r4
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msr cpsr_c, r5 @ change processor mode
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stmfd r6!, {r8-lr}
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msr cpsr_c, r3 @ restore processor mode
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mov sp, r6
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stmfd sp!, {r2,lr} @ it's a bit of a mess, but we will fix that later
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@ order of saved regs now: cpsr, pc + (2/4/8), r8-r14, r0-r7
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mov r0, sp
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b mainHandler
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GEN_HANDLER FIQHandler
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GEN_HANDLER undefinedInstructionHandler
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GEN_HANDLER prefetchAbortHandler
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GEN_HANDLER dataAbortHandler
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.global readMPUConfig
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.type readMPUConfig, %function
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readMPUConfig:
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stmfd sp!, {r4-r8, lr}
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mrc p15,0,r1,c6,c0,0
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mrc p15,0,r2,c6,c1,0
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mrc p15,0,r3,c6,c2,0
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mrc p15,0,r4,c6,c3,0
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mrc p15,0,r5,c6,c4,0
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mrc p15,0,r6,c6,c5,0
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mrc p15,0,r7,c6,c6,0
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mrc p15,0,r8,c6,c7,0
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stmia r0, {r1-r8}
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mrc p15,0,r0,c5,c0,2 @ read data access permission bits
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ldmfd sp!, {r4-r8, pc}
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