151 lines
4.2 KiB
ArmAsm
151 lines
4.2 KiB
ArmAsm
@ This file is part of Luma3DS
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@ Copyright (C) 2016 Aurora Wright, TuxSH
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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@
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@ Additional Terms 7.b of GPLv3 applies to this file: Requiring preservation of specified
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@ reasonable legal notices or author attributions in that material or in the Appropriate Legal
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@ Notices displayed by works containing it.
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.macro GEN_HANDLER name
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.global \name
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.type \name, %function
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\name:
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ldr sp, =#0xffff3000
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stmfd sp!, {r0-r7}
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mov r1, #\@ @ macro expansion counter
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b _commonHandler
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.size \name, . - \name
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.endm
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.text
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.arm
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.align 4
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.global _commonHandler
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.type _commonHandler, %function
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_commonHandler:
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clrex
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cpsid aif
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mrs r2, spsr
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mov r6, sp
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mrs r3, cpsr
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tst r2, #0x20
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bne noFPUInitNorSvcBreak
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sub r0, lr, #4
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stmfd sp!, {lr}
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bl cannotAccessVA
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ldmfd sp!, {lr}
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cmp r0, #0
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bne noFPUInitNorSvcBreak
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ldr r4, [lr, #-4]
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cmp r1, #1
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bne noFPUInit
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lsl r4, #4
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sub r4, #0xc0000000
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cmp r4, #0x30000000
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bcs noFPUInitNorSvcBreak
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fmrx r0, fpexc
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tst r0, #0x40000000
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bne noFPUInitNorSvcBreak
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sub lr, #4
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srsfd sp!, #0x13
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ldmfd sp!, {r0-r7} @ restore context
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cps #0x13 @ FPU init
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stmfd sp, {r0-r3, r11-lr}^
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sub sp, #0x20
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bl . @ will be replaced
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ldmfd sp, {r0-r3, r11-lr}^
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add sp, #0x20
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rfefd sp!
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noFPUInit:
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cmp r1, #2
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bne noFPUInitNorSvcBreak
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ldr r5, =#0xe12fff7f
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cmp r4, r5
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bne noFPUInitNorSvcBreak
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cps #0x13 @ switch to supervisor mode
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cmp r10, #0
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addne sp, #0x28
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ldr r2, [sp, #0x1c] @ implementation details of the official svc handler
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ldr r4, [sp, #0x18]
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msr cpsr_c, r3 @ restore processor mode
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tst r2, #0x20
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addne lr, r4, #2 @ adjust address for later
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moveq lr, r4
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noFPUInitNorSvcBreak:
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ands r4, r2, #0xf @ get the mode that triggered the exception
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moveq r4, #0xf @ usr => sys
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bic r5, r3, #0xf
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orr r5, r4
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msr cpsr_c, r5 @ change processor mode
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stmfd r6!, {r8-lr}
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msr cpsr_c, r3 @ restore processor mode
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mov sp, r6
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stmfd sp!, {r2,lr}
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mrc p15,0,r4,c5,c0,0 @ dfsr
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mrc p15,0,r5,c5,c0,1 @ ifsr
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mrc p15,0,r6,c6,c0,0 @ far
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fmrx r7, fpexc
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fmrx r8, fpinst
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fmrx r9, fpinst2
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stmfd sp!, {r4-r9} @ it's a bit of a mess, but we will fix that later
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@ order of saved regs now: dfsr, ifsr, far, fpexc, fpinst, fpinst2, cpsr, pc + (2/4/8), r8-r14, r0-r7
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bic r3, #(1<<31)
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fmxr fpexc, r3 @ clear the VFP11 exception flag (if it's set)
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mov r0, sp
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mrc p15,0,r2,c0,c0,5 @ CPU ID register
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b mainHandler
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GEN_HANDLER FIQHandler
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GEN_HANDLER undefinedInstructionHandler
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GEN_HANDLER prefetchAbortHandler
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GEN_HANDLER dataAbortHandler
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.global mcuReboot
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.type mcuReboot, %function
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mcuReboot:
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b . @ will be replaced
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.global cleanInvalidateDCacheAndDMB
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.type cleanInvalidateDCacheAndDMB, %function
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cleanInvalidateDCacheAndDMB:
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mov r0, #0
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mcr p15,0,r0,c7,c14,0 @ Clean and Invalidate Entire Data Cache
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mcr p15,0,r0,c7,c10,4 @ Drain Memory Barrier
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bx lr
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.global cannotAccessVA
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.type cannotAccessVA, %function
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cannotAccessVA:
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@ Thanks yellows8 for the hint
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lsr r0, #12
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lsl r0, #12
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mcr p15,0,r0,c7,c8,0 @ VA to PA translation with privileged read permission check
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mrc p15,0,r0,c7,c4,0 @ read PA register
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and r0, #1 @ failure bit
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bx lr
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