425 lines
10 KiB
C
Executable File
425 lines
10 KiB
C
Executable File
// From http://github.com/b1l1s/ctr
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#include "crypto.h"
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#include <stddef.h>
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#include "memory.h"
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#include "fatfs/sdmmc/sdmmc.h"
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#include "fatfs/ff.h"
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//Nand key#2 (0x12C10)
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u8 key2[0x10] = {
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0x42, 0x3F, 0x81, 0x7A, 0x23, 0x52, 0x58, 0x31, 0x6E, 0x75, 0x8E, 0x3A, 0x39, 0x43, 0x2E, 0xD0
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};
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/****************************************************************
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* Crypto Libs
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****************************************************************/
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/* original version by megazig */
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#ifndef __thumb__
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#define BSWAP32(x) {\
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__asm__\
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(\
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"eor r1, %1, %1, ror #16\n\t"\
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"bic r1, r1, #0xFF0000\n\t"\
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"mov %0, %1, ror #8\n\t"\
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"eor %0, %0, r1, lsr #8\n\t"\
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:"=r"(x)\
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:"0"(x)\
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:"r1"\
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);\
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};
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#define ADD_u128_u32(u128_0, u128_1, u128_2, u128_3, u32_0) {\
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__asm__\
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(\
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"adds %0, %4\n\t"\
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"addcss %1, %1, #1\n\t"\
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"addcss %2, %2, #1\n\t"\
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"addcs %3, %3, #1\n\t"\
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: "+r"(u128_0), "+r"(u128_1), "+r"(u128_2), "+r"(u128_3)\
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: "r"(u32_0)\
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: "cc"\
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);\
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}
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#else
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#define BSWAP32(x) {x = __builtin_bswap32(x);}
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#define ADD_u128_u32(u128_0, u128_1, u128_2, u128_3, u32_0) {\
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__asm__\
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(\
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"mov r4, #0\n\t"\
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"add %0, %0, %4\n\t"\
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"adc %1, %1, r4\n\t"\
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"adc %2, %2, r4\n\t"\
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"adc %3, %3, r4\n\t"\
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: "+r"(u128_0), "+r"(u128_1), "+r"(u128_2), "+r"(u128_3)\
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: "r"(u32_0)\
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: "cc", "r4"\
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);\
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}
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#endif /*__thumb__*/
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void aes_setkey(u8 keyslot, const void* key, u32 keyType, u32 mode)
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{
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if(keyslot <= 0x03) return; // Ignore TWL keys for now
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u32* key32 = (u32*)key;
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*REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode;
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*REG_AESKEYCNT = (*REG_AESKEYCNT >> 6 << 6) | keyslot | AES_KEYCNT_WRITE;
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REG_AESKEYFIFO[keyType] = key32[0];
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REG_AESKEYFIFO[keyType] = key32[1];
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REG_AESKEYFIFO[keyType] = key32[2];
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REG_AESKEYFIFO[keyType] = key32[3];
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}
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void aes_use_keyslot(u8 keyslot)
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{
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if(keyslot > 0x3F)
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return;
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*REG_AESKEYSEL = keyslot;
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*REG_AESCNT = *REG_AESCNT | 0x04000000; /* mystery bit */
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}
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void aes_setiv(const void* iv, u32 mode)
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{
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const u32* iv32 = (const u32*)iv;
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*REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode;
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// Word order for IV can't be changed in REG_AESCNT and always default to reversed
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if(mode & AES_INPUT_NORMAL)
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{
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REG_AESCTR[0] = iv32[3];
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REG_AESCTR[1] = iv32[2];
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REG_AESCTR[2] = iv32[1];
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REG_AESCTR[3] = iv32[0];
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}
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else
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{
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REG_AESCTR[0] = iv32[0];
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REG_AESCTR[1] = iv32[1];
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REG_AESCTR[2] = iv32[2];
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REG_AESCTR[3] = iv32[3];
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}
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}
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void aes_advctr(void* ctr, u32 val, u32 mode)
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{
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u32* ctr32 = (u32*)ctr;
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int i;
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if(mode & AES_INPUT_BE)
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{
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for(i = 0; i < 4; ++i) // Endian swap
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BSWAP32(ctr32[i]);
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}
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if(mode & AES_INPUT_NORMAL)
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{
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ADD_u128_u32(ctr32[3], ctr32[2], ctr32[1], ctr32[0], val);
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}
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else
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{
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ADD_u128_u32(ctr32[0], ctr32[1], ctr32[2], ctr32[3], val);
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}
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if(mode & AES_INPUT_BE)
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{
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for(i = 0; i < 4; ++i) // Endian swap
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BSWAP32(ctr32[i]);
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}
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}
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void aes_change_ctrmode(void* ctr, u32 fromMode, u32 toMode)
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{
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u32* ctr32 = (u32*)ctr;
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int i;
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if((fromMode ^ toMode) & AES_CNT_INPUT_ENDIAN)
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{
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for(i = 0; i < 4; ++i)
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BSWAP32(ctr32[i]);
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}
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if((fromMode ^ toMode) & AES_CNT_INPUT_ORDER)
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{
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u32 temp = ctr32[0];
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ctr32[0] = ctr32[3];
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ctr32[3] = temp;
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temp = ctr32[1];
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ctr32[1] = ctr32[2];
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ctr32[2] = temp;
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}
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}
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void aes_batch(void* dst, const void* src, u32 blockCount)
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{
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*REG_AESBLKCNT = blockCount << 16;
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*REG_AESCNT |= AES_CNT_START;
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const u32* src32 = (const u32*)src;
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u32* dst32 = (u32*)dst;
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u32 wbc = blockCount;
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u32 rbc = blockCount;
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while(rbc)
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{
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if(wbc && ((*REG_AESCNT & 0x1F) <= 0xC)) // There's space for at least 4 ints
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{
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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*REG_AESWRFIFO = *src32++;
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wbc--;
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}
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if(rbc && ((*REG_AESCNT & (0x1F << 0x5)) >= (0x4 << 0x5))) // At least 4 ints available for read
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{
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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*dst32++ = *REG_AESRDFIFO;
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rbc--;
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}
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}
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}
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void aes(void* dst, const void* src, u32 blockCount, void* iv, u32 mode, u32 ivMode)
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{
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*REG_AESCNT = mode |
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AES_CNT_INPUT_ORDER | AES_CNT_OUTPUT_ORDER |
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AES_CNT_INPUT_ENDIAN | AES_CNT_OUTPUT_ENDIAN |
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AES_CNT_FLUSH_READ | AES_CNT_FLUSH_WRITE;
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u32 blocks;
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while(blockCount != 0)
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{
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if((mode & AES_ALL_MODES) != AES_ECB_ENCRYPT_MODE
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&& (mode & AES_ALL_MODES) != AES_ECB_DECRYPT_MODE)
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aes_setiv(iv, ivMode);
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blocks = (blockCount >= 0xFFFF) ? 0xFFFF : blockCount;
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// Save the last block for the next decryption CBC batch's iv
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if((mode & AES_ALL_MODES) == AES_CBC_DECRYPT_MODE)
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{
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memcpy(iv, src + (blocks - 1) * AES_BLOCK_SIZE, AES_BLOCK_SIZE);
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aes_change_ctrmode(iv, AES_INPUT_BE | AES_INPUT_NORMAL, ivMode);
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}
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// Process the current batch
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aes_batch(dst, src, blocks);
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// Save the last block for the next encryption CBC batch's iv
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if((mode & AES_ALL_MODES) == AES_CBC_ENCRYPT_MODE)
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{
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memcpy(iv, dst + (blocks - 1) * AES_BLOCK_SIZE, AES_BLOCK_SIZE);
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aes_change_ctrmode(iv, AES_INPUT_BE | AES_INPUT_NORMAL, ivMode);
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}
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// Advance counter for CTR mode
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else if((mode & AES_ALL_MODES) == AES_CTR_MODE)
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aes_advctr(iv, blocks, ivMode);
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src += blocks * AES_BLOCK_SIZE;
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dst += blocks * AES_BLOCK_SIZE;
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blockCount -= blocks;
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}
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}
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void sha_wait_idle()
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{
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while(*REG_SHA_CNT & 1);
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}
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void sha(void* res, const void* src, u32 size, u32 mode)
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{
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sha_wait_idle();
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*REG_SHA_CNT = mode | SHA_CNT_OUTPUT_ENDIAN | SHA_NORMAL_ROUND;
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const u32* src32 = (const u32*)src;
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int i;
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while(size >= 0x40)
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{
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sha_wait_idle();
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for(i = 0; i < 4; ++i)
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{
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*REG_SHA_INFIFO = *src32++;
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*REG_SHA_INFIFO = *src32++;
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*REG_SHA_INFIFO = *src32++;
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*REG_SHA_INFIFO = *src32++;
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}
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size -= 0x40;
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}
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sha_wait_idle();
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memcpy((void*)REG_SHA_INFIFO, src32, size);
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*REG_SHA_CNT = (*REG_SHA_CNT & ~SHA_NORMAL_ROUND) | SHA_FINAL_ROUND;
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while(*REG_SHA_CNT & SHA_FINAL_ROUND);
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sha_wait_idle();
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u32 hashSize = SHA_256_HASH_SIZE;
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if(mode == SHA_224_MODE)
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hashSize = SHA_224_HASH_SIZE;
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else if(mode == SHA_1_MODE)
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hashSize = SHA_1_HASH_SIZE;
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memcpy(res, (void*)REG_SHA_HASH, hashSize);
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}
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void rsa_wait_idle()
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{
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while(*REG_RSA_CNT & 1);
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}
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void rsa_use_keyslot(u32 keyslot)
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{
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*REG_RSA_CNT = (*REG_RSA_CNT & ~RSA_CNT_KEYSLOTS) | (keyslot << 4);
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}
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void rsa_setkey(u32 keyslot, const void* mod, const void* exp, u32 mode)
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{
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rsa_wait_idle();
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*REG_RSA_CNT = (*REG_RSA_CNT & ~RSA_CNT_KEYSLOTS) | (keyslot << 4) | RSA_IO_BE | RSA_IO_NORMAL;
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u32 size = mode * 4;
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volatile u32* keyslotCnt = REG_RSA_SLOT0 + (keyslot << 4);
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keyslotCnt[0] &= ~(RSA_SLOTCNT_KEY_SET | RSA_SLOTCNT_WPROTECT);
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keyslotCnt[1] = mode;
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memcpy((void*)REG_RSA_MOD_END - size, mod, size);
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if(exp == NULL)
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{
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size -= 4;
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while(size)
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{
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*REG_RSA_EXPFIFO = 0;
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size -= 4;
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}
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*REG_RSA_EXPFIFO = 0x01000100; // 0x00010001 byteswapped
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}
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else
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{
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const u32* exp32 = (const u32*)exp;
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while(size)
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{
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*REG_RSA_EXPFIFO = *exp32++;
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size -= 4;
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}
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}
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}
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int rsa_iskeyset(u32 keyslot)
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{
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return *(REG_RSA_SLOT0 + (keyslot << 4)) & 1;
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}
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void rsa(void* dst, const void* src, u32 size)
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{
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u32 keyslot = (*REG_RSA_CNT & RSA_CNT_KEYSLOTS) >> 4;
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if(rsa_iskeyset(keyslot) == 0)
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return;
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rsa_wait_idle();
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*REG_RSA_CNT |= RSA_IO_BE | RSA_IO_NORMAL;
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// Pad the message with zeroes so that it's a multiple of 8
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// and write the message with the end aligned with the register
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u32 padSize = ((size + 7) & ~7) - size;
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memset((void*)REG_RSA_TXT_END - (size + padSize), 0, padSize);
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memcpy((void*)REG_RSA_TXT_END - size, src, size);
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// Start
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*REG_RSA_CNT |= RSA_CNT_START;
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rsa_wait_idle();
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memcpy(dst, (void*)REG_RSA_TXT_END - size, size);
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}
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int rsa_verify(const void* data, u32 size, const void* sig, u32 mode)
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{
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u8 dataHash[SHA_256_HASH_SIZE];
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sha(dataHash, data, size, SHA_256_MODE);
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u8 decSig[0x100]; // Way too big, need to request a work area
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u32 sigSize = mode * 4;
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rsa(decSig, sig, sigSize);
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return memcmp(dataHash, decSig + (sigSize - SHA_256_HASH_SIZE), SHA_256_HASH_SIZE) == 0;
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}
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/****************************************************************
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* Nand/FIRM Crypto stuff
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****************************************************************/
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//Get Nand CTR key
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void getNandCTR(u8 *buf, u8 console) {
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u8 *addr = console ? (u8*)0x080D8BBC : (u8*)0x080D797C;
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u8 keyLen = 0x10; //CTR length
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addr += 0x0F;
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while (keyLen --) { *(buf++) = *(addr--); }
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}
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//Read firm0 from NAND and write to buffer
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void nandFirm0(u8 *outbuf, const u32 size, u8 console){
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u8 CTR[0x10];
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getNandCTR(CTR, console);
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aes_advctr(CTR, 0x0B130000/0x10, AES_INPUT_BE | AES_INPUT_NORMAL);
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sdmmc_nand_readsectors(0x0B130000 / 0x200, size / 0x200, outbuf);
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aes_use_keyslot(0x06);
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aes(outbuf, outbuf, size / AES_BLOCK_SIZE, CTR, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
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}
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//Decrypts the N3DS arm9bin
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void decArm9Bin(void *armHdr, u8 mode){
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//Firm keys
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u8 keyX[0x10];
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u8 keyY[0x10];
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u8 CTR[0x10];
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u32 slot = mode ? 0x16 : 0x15;
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//Setup keys needed for arm9bin decryption
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memcpy((u8*)keyY, (void *)(armHdr+0x10), 0x10);
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memcpy((u8*)CTR, (void *)(armHdr+0x20), 0x10);
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u32 size = atoi((void *)(armHdr+0x30));
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if(mode){
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//Set 0x11 to key2 for the arm9bin and misc keys
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aes_setkey(0x11, (u8*)key2, AES_KEYNORMAL, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_use_keyslot(0x11);
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aes((u8*)keyX, (void *)(armHdr+0x60), 1, NULL, AES_ECB_DECRYPT_MODE, 0);
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aes_setkey(slot, (u8*)keyX, AES_KEYX, AES_INPUT_BE | AES_INPUT_NORMAL);
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}
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aes_setkey(slot, (u8*)keyY, AES_KEYY, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_setiv((u8*)CTR, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_use_keyslot(slot);
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//Decrypt arm9bin
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aes((void *)(armHdr+0x800), (void *)(armHdr+0x800), size/AES_BLOCK_SIZE, CTR, AES_CTR_MODE, AES_INPUT_BE | AES_INPUT_NORMAL);
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}
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//Sets the N3DS 9.6 KeyXs
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void setKeyXs(void *armHdr){
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//Set keys 0x19..0x1F keyXs
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u8* decKey = (void *)(armHdr+0x89824);
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aes_setkey(0x11, (u8*)key2, AES_KEYNORMAL, AES_INPUT_BE | AES_INPUT_NORMAL);
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aes_use_keyslot(0x11);
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for(u32 slot = 0x19; slot < 0x20; slot++){
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aes(decKey, (void *)(armHdr+0x89814), 1, NULL, AES_ECB_DECRYPT_MODE, 0);
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aes_setkey(slot, (u8*)decKey, AES_KEYX, AES_INPUT_BE | AES_INPUT_NORMAL);
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*(u8*)(armHdr+0x89814+0xF) += 1;
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}
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} |