208 lines
4.3 KiB
ArmAsm
208 lines
4.3 KiB
ArmAsm
; Code originally from delebile and mid-kid
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.arm.little
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copy_launch_stub_stack_top equ 0x01FFB800
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copy_launch_stub_stack_bottom equ 0x01FFA800
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copy_launch_stub_addr equ 0x01FF9000
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argv_addr equ (copy_launch_stub_stack_bottom - 0x100)
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fname_addr equ (copy_launch_stub_stack_bottom - 0x200)
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low_tid_addr equ (copy_launch_stub_stack_bottom - 0x300)
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firm_addr equ 0x20001000
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firm_maxsize equ 0x07FFF000
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.create "build/reboot.bin", 0
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.arm
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; Interesting registers and locations to keep in mind, set just before this code is ran:
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; - r1: FIRM path in exefs.
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; - r7 (or r8): pointer to file object
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; - *r7: vtable
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; - *(vtable + 0x28): fread function
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; - *(r7 + 8): file handle
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sub r7, r0, #8
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mov r8, r1
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pxi_wait_recv:
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ldr r2, =0x44846
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ldr r0, =0x10008000
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readPxiLoop1:
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ldrh r1, [r0, #4]
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lsls r1, #0x17
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bmi readPxiLoop1
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ldr r0, [r0, #0xC]
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cmp r0, r2
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bne pxi_wait_recv
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; Open file
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add r0, r7, #8
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adr r1, fname
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mov r2, #1
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ldr r6, [fopen]
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orr r6, 1
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blx r6
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cmp r0, #0
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bne panic
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; Read file
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mov r0, r7
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adr r1, bytes_read
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ldr r2, =firm_addr
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ldr r3, =firm_maxsize
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ldr r6, [r7]
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ldr r6, [r6, #0x28]
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blx r6
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; Copy the low TID (in UTF-16) of the wanted firm
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ldr r0, =low_tid_addr
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add r1, r8, #0x1A
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mov r2, #0x10
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bl memcpy16
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; Copy argv[0]
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ldr r0, =fname_addr
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adr r1, fname
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mov r2, #82
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bl memcpy16
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ldr r0, =argv_addr
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ldr r1, =fname_addr
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ldr r2, =low_tid_addr
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stmia r0, {r1, r2}
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; Set kernel state
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mov r0, #0
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mov r1, #0
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mov r2, #0
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mov r3, #0
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swi 0x7C
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goto_reboot:
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; Jump to reboot code
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ldr r0, =(kernelcode_start - goto_reboot - 12)
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add r0, pc ; pc is two instructions ahead of the instruction being executed (12 = 2*4 + 4)
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swi 0x7B
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die:
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b die
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memcpy16:
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cmp r2, #0
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bxeq lr
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add r2, r0, r2
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copy_loop16:
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ldrh r3, [r1], #2
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strh r3, [r0], #2
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cmp r0, r2
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blo copy_loop16
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bx lr
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panic:
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mov r1, r0 ; unused register
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mov r0, #0
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swi 0x3C ; svcBreak(USERBREAK_PANIC)
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b die
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bytes_read: .word 0
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fopen: .ascii "OPEN"
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.pool
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.area 2*(80+1), 0
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fname: .ascii "FILE"
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.endarea
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.align 4
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kernelcode_start:
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msr cpsr_cxsf, #0xD3 ; disable interrupts and clear flags
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ldr sp, =copy_launch_stub_stack_top
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ldr r0, =copy_launch_stub_addr
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adr r1, copy_launch_stub
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mov r2, #(copy_launch_stub_end - copy_launch_stub)
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bl memcpy32
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; Disable MPU
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ldr r0, =0x42078 ; alt vector select, enable itcm
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mcr p15, 0, r0, c1, c0, 0
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bl flushCaches
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ldr r0, =copy_launch_stub_addr
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bx r0
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copy_launch_stub:
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ldr r4, =firm_addr
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mov r5, #0
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load_section_loop:
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; Such checks. Very ghetto. Wow.
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add r3, r4, #0x40
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add r3, r5,lsl #5
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add r3, r5,lsl #4
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ldmia r3, {r6-r8}
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cmp r8, #0
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movne r0, r7
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addne r1, r4, r6
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movne r2, r8
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blne memcpy32
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add r5, #1
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cmp r5, #4
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blo load_section_loop
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mov r0, #2 ; argc
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ldr r1, =argv_addr ; argv
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ldr r2, =0xBABE ; magic word
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mov r5, #0x20000000
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ldr r6, [r4, #0x08]
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str r6, [r5, #-4] ; store arm11 entrypoint
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ldr lr, [r4, #0x0c]
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bx lr
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memcpy32:
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add r2, r0, r2
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copy_loop32:
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ldr r3, [r1], #4
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str r3, [r0], #4
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cmp r0, r2
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blo copy_loop32
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bx lr
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.pool
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copy_launch_stub_end:
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flushCaches:
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; Clean and flush data cache
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mov r1, #0 ; segment counter
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outer_loop:
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mov r0, #0 ; line counter
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inner_loop:
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orr r2, r1, r0 ; generate segment and line address
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mcr p15, 0, r2, c7, c14, 2 ; clean and flush the line
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add r0, #0x20 ; increment to next line
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cmp r0, #0x400
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bne inner_loop
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add r1, #0x40000000
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cmp r1, #0
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bne outer_loop
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; Drain write buffer
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mcr p15, 0, r1, c7, c10, 4
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; Flush instruction cache
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mcr p15, 0, r1, c7, c5, 0
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bx lr
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.close
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