7dbded99a2
- Gotten rid of the patched FIRMs, AuReiNand now finds and loads all the FIRMs from CTRNAND by default. If you are booting an emuNAND, the FIRMs will be loaded from its CTRNAND. This also applies to AGB and TWL FIRM, and allows for a very fast boot with no firmware files on the SD card. - If for some reason (like using NTR) you do not want to use the CTRNAND FIRM, you can place a firmware.bin in the aurei folder and it will be loaded just for the default NAND. - The way AuReiNand works has changed. Now you can specify to autoboot SysNAND or not, and a NAND is no more tied to a FIRM (since 9.0 FIRM is autodetected). If you press nothing the default NAND is booted with its own FIRM, L boots the non-default NAND with its own FIRM, R boots EmuNAND with the SysNAND FIRM if you picked "Updated SysNAND", and vice-versa. - In order for AuReiNand to handle FIRM reboots, the .bin path needs to be hardcoded in the program. The default is /arm9loaderhax.bin (the AuReiNand.dat is also supported for 9.0 people). A PC tool was written to make changing the path easier. - Bug fixes and stuff I forgot. - Gelex is a saint.
59 lines
1.6 KiB
ArmAsm
59 lines
1.6 KiB
ArmAsm
.section .text.start
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.align 4
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.global _start
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_start:
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b start
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.word 0
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start:
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@ Change the stack pointer
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mov sp, #0x27000000
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@ Give read/write access to all the memory regions
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ldr r5, =0x33333333
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mcr p15, 0, r5, c5, c0, 2 @ write data access
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mcr p15, 0, r5, c5, c0, 3 @ write instruction access
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@ Sets MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k
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ldr r1, =0x01FF801D @ 01ff8000 32k
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ldr r2, =0x08000027 @ 08000000 1M
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ldr r3, =0x10000021 @ 10000000 128k
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ldr r4, =0x10100025 @ 10100000 512k
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ldr r5, =0x20000035 @ 20000000 128M
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ldr r6, =0x1FF00027 @ 1FF00000 1M
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ldr r7, =0x1800002D @ 18000000 8M
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mov r0, #0x25
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mcr p15, 0, r0, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r0, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r0, c2, c0, 1 @ Inst cacheable 0, 2, 5
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@ Enable caches
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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orr r4, r4, #(1<<12) @ - instruction cache enable
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orr r4, r4, #(1<<2) @ - data cache enable
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orr r4, r4, #(1<<0) @ - mpu enable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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@ Flush caches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
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mcr p15, 0, r0, c7, c6, 0 @ flush D-cache
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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@ Fix mounting of SDMC
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ldr r0, =0x10000020
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mov r1, #0x340
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str r1, [r0]
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b main
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