167 lines
5.3 KiB
ArmAsm
167 lines
5.3 KiB
ArmAsm
@ This file is part of Luma3DS
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@ Copyright (C) 2016-2020 Aurora Wright, TuxSH
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@
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@ This program is free software: you can redistribute it and/or modify
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@ it under the terms of the GNU General Public License as published by
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@ the Free Software Foundation, either version 3 of the License, or
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@ (at your option) any later version.
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@
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@ This program is distributed in the hope that it will be useful,
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@ but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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@ GNU General Public License for more details.
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@
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@ You should have received a copy of the GNU General Public License
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@ along with this program. If not, see <http://www.gnu.org/licenses/>.
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@
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@ Additional Terms 7.b and 7.c of GPLv3 apply to this file:
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@ * Requiring preservation of specified reasonable legal notices or
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@ author attributions in that material or in the Appropriate Legal
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@ Notices displayed by works containing it.
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@ * Prohibiting misrepresentation of the origin of that material,
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@ or requiring that modified versions of such material be marked in
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@ reasonable ways as different from the original version.
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.section .text.start, "ax", %progbits
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.align 4
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.global _start
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_start:
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@ Disable interrupts and switch to supervisor mode (also clear flags)
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msr cpsr_cxsf, #0xD3
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@ Check if r0-r2 are 0 (r0-sp are supposed to be 0), and for regions 0, 5 and 7 of the MPU config
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@ This is not foolproof but should work well enough
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cmp r0, #0
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cmpeq r1, #0
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cmpeq r2, #0
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ldreq r4, =0x20000035
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mrceq p15, 0, r5, c6, c0, 0
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cmpeq r4, r5
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mrceq p15, 0, r5, c6, c5, 0
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ldreq r4, =0x07FF801D
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cmpeq r4, r5
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mrceq p15, 0, r5, c6, c7, 0
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ldreq r4, =0x1FFFE019
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cmpeq r4, r5
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ldreq r2, =0xB002
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mov r9, r0
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mov r10, r1
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mov r11, r2
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@ Change the stack pointer
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mov sp, #0x08100000
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@ Disable caches / MPU
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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bic r4, #(1<<16) @ - DTCM disable
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bic r4, #(1<<12) @ - instruction cache disable
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bic r4, #(1<<2) @ - data cache disable
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bic r4, #(1<<0) @ - MPU disable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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@ Invalidate both caches, discarding any data they may contain,
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@ then drain the write buffer
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mov r4, #0
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mcr p15, 0, r4, c7, c5, 0
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mcr p15, 0, r4, c7, c6, 0
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mcr p15, 0, r4, c7, c10, 4
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@ Give read/write access to all the memory regions
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Set MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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ldr r1, =0xFFF0001B @ fff00000 16k | dtcm
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ldr r2, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r3, =0x08000027 @ 08000000 1M | arm9 mem
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ldr r4, =0x10000029 @ 10000000 2M | io mem (Arm9 / first 2MB)
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ldr r5, =0x20000035 @ 20000000 128M | fcram
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ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r8, #0x29
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 3, 5
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 3, 5
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 3, 5
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@ Set DTCM address and size to the default values
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ldr r1, =0xFFF0000A @ set DTCM address and size
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mcr p15, 0, r1, c9, c1, 0 @ set the dtcm Region Register
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@ Enable caches / MPU / ITCM
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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orr r0, r0, #(1<<18) @ - ITCM enable
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orr r0, r0, #(1<<16) @ - DTCM enable
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orr r0, r0, #(1<<13) @ - alternate exception vectors enable
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orr r0, r0, #(1<<12) @ - instruction cache enable
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orr r0, r0, #(1<<2) @ - data cache enable
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orr r0, r0, #(1<<0) @ - MPU enable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Clear BSS
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ldr r0, =__bss_start__
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mov r1, #0
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ldr r2, =__bss_end__
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sub r2, r0
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bl memset
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bl __libc_init_array
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mov r0, r9
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mov r1, r10
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mov r2, r11
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b main
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.pool
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.section .chainloader.text.start, "ax", %progbits
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.align 4
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.global chainload
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.type chainload, %function
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chainload:
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ldr sp, =__itcm_stack_top__
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b chainloader_main
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.pool
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.global disableMpuAndJumpToEntrypoints
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.type disableMpuAndJumpToEntrypoints, %function
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disableMpuAndJumpToEntrypoints:
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mov r4, r0
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mov r5, r1
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mov r6, r2
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mov r7, r3
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@ Flush caches
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ldr r12, =0xFFFF0830
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blx r12
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ldr r12, =0xFFFF0AB4
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blx r12
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@ Disable caches / MPU
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, #(1<<12) @ - instruction cache disable
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bic r0, #(1<<2) @ - data cache disable
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bic r0, #(1<<0) @ - MPU disable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Set the Arm11 entrypoint
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mov r0, #0x20000000
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str r7, [r0, #-4]
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@ Jump to the Arm9 entrypoint
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mov r0, r4
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mov r1, r5
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ldr r2, =0x3BEEF
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bx r6
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.pool
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