49 lines
1.3 KiB
ArmAsm
49 lines
1.3 KiB
ArmAsm
.section .text.start
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.align 4
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.global _start
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_start:
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@ Change the stack pointer
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mov sp, #0x27000000
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@ Sets MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k
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ldr r1, =0x01FF801D @ 01ff8000 32k
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ldr r2, =0x08000027 @ 08000000 1M
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ldr r3, =0x10000021 @ 10000000 128k
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ldr r4, =0x10100025 @ 10100000 512k
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ldr r5, =0x20000035 @ 20000000 128M
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ldr r6, =0x2800801B @ 28008000 16k
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ldr r7, =0x1800002D @ 18000000 8M
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ldr r8, =0x33333336
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ldr r9, =0x60600666
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mov r10, #0x25
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mov r11, #0x25
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mov r12, #0x25
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r8, c5, c0, 2 @ Enable data r/w for all regions
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mcr p15, 0, r9, c5, c0, 3 @ Enable inst read for 0, 1, 2, 5, 7
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mcr p15, 0, r10, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r11, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r12, c2, c0, 1 @ Inst cacheable 0, 2, 5
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@ Enables all the settings we specified above
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ldr r0, =0x5307D
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mcr p15, 0, r0, c1, c0, 0 @ cp15 ctl register enable mpu, enable cache and use alt vector table
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@ Undocumented: Fixes mounting of SDMC
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ldr r0, =0x10000020
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mov r1, #0x340
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str r1, [r0]
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bl main
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.die:
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b .die
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