21db0d45bd
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147 lines
4.7 KiB
C
147 lines
4.7 KiB
C
/*
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* This file is part of Luma3DS
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* Copyright (C) 2016-2017 Aurora Wright, TuxSH
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Additional Terms 7.b and 7.c of GPLv3 apply to this file:
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* * Requiring preservation of specified reasonable legal notices or
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* author attributions in that material or in the Appropriate Legal
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* Notices displayed by works containing it.
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* * Prohibiting misrepresentation of the origin of that material,
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* or requiring that modified versions of such material be marked in
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* reasonable ways as different from the original version.
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*/
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#include "kernel_extension.h"
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#include "kernel_extension_setup.h"
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#define MPCORE_REGS_BASE ((u32)PA_PTR(0x17E00000))
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#define MPCORE_GID_REGS_BASE (MPCORE_REGS_BASE + 0x1000)
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#define MPCORE_GID_SGI (*(vu32 *)(MPCORE_GID_REGS_BASE + 0xF00))
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struct Parameters
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{
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void (*SGI0HandlerCallback)(struct Parameters *, u32 *);
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void *interruptManager;
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u32 *L2MMUTable; // bit31 mapping
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void (*initFPU)(void);
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void (*mcuReboot)(void);
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void (*coreBarrier)(void);
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u32 TTBCR;
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u32 L1MMUTableAddrs[4];
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u32 kernelVersion;
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struct CfwInfo
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{
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char magic[4];
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u8 versionMajor;
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u8 versionMinor;
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u8 versionBuild;
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u8 flags;
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u32 commitHash;
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u32 config;
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} __attribute__((packed)) info;
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};
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static void K_SGI0HandlerCallback(volatile struct Parameters *p)
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{
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u32 L1MMUTableAddr;
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vu32 *L1MMUTable;
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u32 coreId;
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__asm__ volatile("cpsid aif"); // disable interrupts
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p->coreBarrier();
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__asm__ volatile("mrc p15, 0, %0, c0, c0, 5" : "=r"(coreId));
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coreId &= 3;
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__asm__ volatile("mrc p15, 0, %0, c2, c0, 1" : "=r"(L1MMUTableAddr));
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L1MMUTableAddr &= ~0x3FFF;
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p->L1MMUTableAddrs[coreId] = L1MMUTableAddr;
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L1MMUTable = (vu32 *)(L1MMUTableAddr | (1 << 31));
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// Actually map the kernel ext
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u32 L2MMUTableAddr = (u32)(p->L2MMUTable) & ~(1 << 31);
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L1MMUTable[0x40000000 >> 20] = L2MMUTableAddr | 1;
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__asm__ __volatile__("mcr p15, 0, %[val], c7, c10, 4" :: [val] "r" (0) : "memory");
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((void (*)(volatile struct Parameters *))0x40000000)(p);
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p->coreBarrier();
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}
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static u32 ALIGN(0x400) L2MMUTableFor0x40000000[256] = { 0 };
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u32 TTBCR;
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static void K_ConfigureSGI0(void)
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{
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// see /patches/k11MainHook.s
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u32 *off;
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u32 *initFPU, *mcuReboot, *coreBarrier;
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// Search for stuff in the 0xFFFF0000 page
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for(initFPU = (u32 *)0xFFFF0000; initFPU < (u32 *)0xFFFF1000 && *initFPU != 0xE1A0D002; initFPU++);
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initFPU += 3;
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for(mcuReboot = initFPU; mcuReboot < (u32 *)0xFFFF1000 && *mcuReboot != 0xE3A0A0C2; mcuReboot++);
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mcuReboot--;
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coreBarrier = (u32 *)decodeARMBranch(mcuReboot - 4);
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for(off = mcuReboot; off < (u32 *)0xFFFF1000 && *off != 0x726C6468; off++); // "hdlr"
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volatile struct Parameters *p = (struct Parameters *)PA_FROM_VA_PTR(off); // Caches? What are caches?
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p->SGI0HandlerCallback = (void (*)(struct Parameters *, u32 *))PA_FROM_VA_PTR(K_SGI0HandlerCallback);
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p->L2MMUTable = (u32 *)PA_FROM_VA_PTR(L2MMUTableFor0x40000000);
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p->initFPU = (void (*) (void))initFPU;
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p->mcuReboot = (void (*) (void))mcuReboot;
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p->coreBarrier = (void (*) (void))coreBarrier;
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__asm__ volatile("mrc p15, 0, %0, c2, c0, 2" : "=r"(TTBCR));
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p->TTBCR = TTBCR;
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p->kernelVersion = *(vu32 *)0x1FF80000;
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// Now let's configure the L2 table
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//4KB extended small pages: [SYS:RW USR:-- X TYP:NORMAL SHARED OUTER NOCACHE, INNER CACHED WB WA]
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for(u32 offset = 0; offset < kernel_extension_size; offset += 0x1000)
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L2MMUTableFor0x40000000[offset >> 12] = (u32)convertVAToPA(kernel_extension + offset) | 0x516;
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}
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static void K_SendSGI0ToAllCores(void)
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{
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MPCORE_GID_SGI = 0xF0000; // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/CACGDJJC.html
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}
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static inline void flushAllCaches(void)
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{
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svcUnmapProcessMemory(CUR_PROCESS_HANDLE, 0, 0); // this SVC flush both caches entirely (and properly) even when returing an error
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}
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void installKernelExtension(void)
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{
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svc0x2F(K_ConfigureSGI0);
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flushAllCaches();
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svc0x2F(K_SendSGI0ToAllCores);
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flushAllCaches();
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}
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