Merge branch 'master' into developer
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commit
fcb8edffdf
@ -6,5 +6,8 @@ void main(void)
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memcpy(payloadAddress, (void*)0x24F00000, *(u32 *)0x24FFFF04);
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((void (*)(void))0xFFFF0830)(); //Clean and flush the entire DCache, then drain the write buffer
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((void (*)(void))0xFFFF0AB4)(); //Flush the entire ICache
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((void (*)())payloadAddress)();
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}
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@ -8,11 +8,15 @@
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/***
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The following functions flush the data cache, then waits for all memory transfers to be finished.
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The data cache MUST be flushed before doing one of the following:
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The data cache and/or the instruction cache MUST be flushed before doing one of the following:
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- rebooting
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- powering down
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- setting the ARM11 entrypoint to execute a function
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- jumping to a payload
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***/
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void flushEntireDCache(void);
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void flushEntireDCache(void); //actually: "clean and flush"
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void flushDCacheRange(void *startAddress, u32 size);
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void flushEntireICache(void);
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void flushICacheRange(void *startAddress, u32 size);
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@ -15,6 +15,7 @@ flushEntireDCache:
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@ Adpated from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0155a/ch03s03s05.html ,
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@ and https://github.com/gemarcano/libctr9_io/blob/master/src/ctr_system_ARM.c#L39 as well
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@ Note: ARM's example is actually for a 8KB DCache (which is what the 3DS has)
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@ Implemented in bootROM at address 0xffff0830
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mov r1, #0 @ segment counter
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outer_loop:
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@ -31,21 +32,49 @@ flushEntireDCache:
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cmp r1, #0
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bne outer_loop
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r1, c7, c10, 4 @ drain write buffer
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bx lr
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.global flushDCacheRange
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.type flushDCacheRange, %function
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flushDCacheRange:
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@ Implemented in bootROM at address 0xffff08a0
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add r1, r0, r1 @ end address
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bic r0, #0x1f @ align source address to cache line size (32 bytes)
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flush_range_loop:
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flush_dcache_range_loop:
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mcr p15, 0, r0, c7, c14, 1 @ clean and flush the line corresponding to the address r0 is holding
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add r0, #0x20
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cmp r0, r1
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bls flush_range_loop
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blt flush_dcache_range_loop
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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bx lr
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.global flushEntireICache
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.type flushEntireICache, %function
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flushEntireICache:
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@ Implemented in bootROM at address 0xffff0ab4
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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bx lr
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.global flushICacheRange
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.type flushICacheRange, %function
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flushICacheRange:
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@ Implemented in bootROM at address 0xffff0ac0
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add r1, r0, r1 @ end address
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bic r0, #0x1f @ align source address to cache line size (32 bytes)
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flush_icache_range_loop:
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mcr p15, 0, r0, c7, c5, 1 @ flush the line corresponding to the address r0 is holding
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add r0, #0x20
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cmp r0, r1
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blt flush_icache_range_loop
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bx lr
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@ -426,6 +426,7 @@ static inline void launchFirm(FirmwareType firmType, u32 isFirmlaunch)
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}
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flushEntireDCache(); //Ensure that all memory transfers have completed and that the data cache has been flushed
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flushEntireICache();
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//Set ARM11 kernel entrypoint
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*arm11 = (u32)firm->arm11Entry;
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@ -4,6 +4,7 @@
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#include "fs.h"
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#include "memory.h"
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#include "cache.h"
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#include "screen.h"
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#include "fatfs/ff.h"
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#include "buttons.h"
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@ -88,6 +89,8 @@ void loadPayload(u32 pressed)
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if(pattern[0] == 'n') f_unlink(path);
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flushDCacheRange(loaderAddress, loader_size);
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flushICacheRange(loaderAddress, loader_size);
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((void (*)())loaderAddress)();
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}
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}
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@ -120,7 +120,7 @@ void clearScreens(void)
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WAIT_FOR_ARM9();
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}
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flushDCacheRange(fb, sizeof(struct fb));
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flushDCacheRange((void *)fb, sizeof(struct fb));
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invokeArm11Function(ARM11);
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}
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@ -229,7 +229,7 @@ u32 initScreens(void)
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if(needToInit)
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{
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flushDCacheRange(&config, 4);
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flushDCacheRange(fb, sizeof(struct fb));
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flushDCacheRange((void *)fb, sizeof(struct fb));
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invokeArm11Function(ARM11);
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//Turn on backlight
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