External .code section loading for titles and some refactoring
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ae1033d975
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@ -125,21 +125,50 @@ static u32 loadConfig(void)
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return config;
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return config;
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}
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}
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static void progIdToStr(char *strEnd, u64 progId)
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{
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while(progId)
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{
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static const char hexDigits[] = "0123456789ABCDEF";
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*strEnd-- = hexDigits[(u32)(progId & 0xF)];
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progId >>= 4;
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}
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}
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static int loadTitleCodeSection(u64 progId, u8 *code, u32 size)
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{
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/* Here we look for "/luma/code_sections/[u64 titleID in hex, uppercase].bin"
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If it exists it should be a decompressed binary code file */
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char path[] = "/luma/code_sections/0000000000000000.bin";
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progIdToStr(path + 35, progId);
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IFile file;
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Result ret = fileOpen(&file, ARCHIVE_SDMC, path, FS_OPEN_READ);
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if(R_SUCCEEDED(ret))
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{
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u64 fileSize, total;
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ret = IFile_GetSize(&file, &fileSize);
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if(!R_SUCCEEDED(ret) || fileSize > size) return -1;
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ret = IFile_Read(&file, &total, code, fileSize);
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IFile_Close(&file);
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if(!R_SUCCEEDED(ret)) return -1;
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else if(total < fileSize) return -2; //Shouldn't happen
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}
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return ret;
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}
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static int loadTitleLocaleConfig(u64 progId, u8 *regionId, u8 *languageId)
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static int loadTitleLocaleConfig(u64 progId, u8 *regionId, u8 *languageId)
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{
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{
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/* Here we look for "/luma/locales/[u64 titleID in hex, uppercase].txt"
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/* Here we look for "/luma/locales/[u64 titleID in hex, uppercase].txt"
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If it exists it should contain, for example, "EUR IT" */
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If it exists it should contain, for example, "EUR IT" */
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char path[] = "/luma/locales/0000000000000000.txt";
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char path[] = "/luma/locales/0000000000000000.txt";
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progIdToStr(path + 29, progId);
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u32 i = 29;
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while(progId)
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{
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static const char hexDigits[] = "0123456789ABCDEF";
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path[i--] = hexDigits[(u32)(progId & 0xF)];
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progId >>= 4;
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}
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IFile file;
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IFile file;
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Result ret = fileOpen(&file, ARCHIVE_SDMC, path, FS_OPEN_READ);
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Result ret = fileOpen(&file, ARCHIVE_SDMC, path, FS_OPEN_READ);
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@ -522,6 +551,9 @@ void patchCode(u64 progId, u8 *code, u32 size)
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if(tidHigh == 0x0004000)
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if(tidHigh == 0x0004000)
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{
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{
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//External .code section loading
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if(loadTitleCodeSection(progId, code, size) == -2) svcBreak(USERBREAK_ASSERT);
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//Language emulation
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//Language emulation
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u8 regionId = 0xFF,
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u8 regionId = 0xFF,
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languageId = 0xFF;
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languageId = 0xFF;
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@ -24,7 +24,7 @@ void configureCFW(const char *configPath)
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"( ) SysNAND is updated (A9LH-only)",
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"( ) SysNAND is updated (A9LH-only)",
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"( ) Force A9LH detection",
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"( ) Force A9LH detection",
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"( ) Use second EmuNAND as default",
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"( ) Use second EmuNAND as default",
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"( ) Enable region/language emulation",
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"( ) Enable region/language emu. and external .code loading",
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"( ) Show current NAND in System Settings",
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"( ) Show current NAND in System Settings",
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"( ) Show GBA boot screen in patched AGB_FIRM",
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"( ) Show GBA boot screen in patched AGB_FIRM",
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"( ) Enable splash screen with no screen-init" };
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"( ) Enable splash screen with no screen-init" };
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@ -11,16 +11,16 @@ start:
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mov sp, #0x27000000
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mov sp, #0x27000000
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@ Disable caches / mpu
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@ Disable caches / mpu
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r4, #(1<<12) @ - instruction cache disable
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bic r0, #(1<<12) @ - instruction cache disable
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bic r4, #(1<<2) @ - data cache disable
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bic r0, #(1<<2) @ - data cache disable
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bic r4, #(1<<0) @ - mpu disable
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bic r0, #(1<<0) @ - mpu disable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Give read/write access to all the memory regions
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@ Give read/write access to all the memory regions
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ldr r5, =0x33333333
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ldr r0, =0x33333333
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mcr p15, 0, r5, c5, c0, 2 @ write data access
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mcr p15, 0, r0, c5, c0, 2 @ write data access
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mcr p15, 0, r5, c5, c0, 3 @ write instruction access
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mcr p15, 0, r0, c5, c0, 3 @ write instruction access
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@ Sets MPU permissions and cache settings
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@ Sets MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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@ -31,9 +31,7 @@ start:
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ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r10, #0x25
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mov r8, #0x25
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mov r11, #0x25
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mov r12, #0x25
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r2, c6, c2, 0
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@ -42,28 +40,28 @@ start:
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r10, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r8, c3, c0, 0 @ Write bufferable 0, 2, 5
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mcr p15, 0, r11, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r8, c2, c0, 0 @ Data cacheable 0, 2, 5
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mcr p15, 0, r12, c2, c0, 1 @ Inst cacheable 0, 2, 5
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mcr p15, 0, r8, c2, c0, 1 @ Inst cacheable 0, 2, 5
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@ Enable dctm
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@ Enable dctm
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ldr r1, =0x3000800A @ set dtcm
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ldr r0, =0x3000800A @ set dtcm
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mcr p15, 0, r1, c9, c1, 0 @ set the dtcm Region Register
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mcr p15, 0, r0, c9, c1, 0 @ set the dtcm Region Register
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@ Enable caches
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@ Enable caches
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mrc p15, 0, r4, c1, c0, 0 @ read control register
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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orr r4, r4, #(1<<18) @ - itcm enable
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orr r0, r0, #(1<<18) @ - itcm enable
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orr r4, r4, #(1<<16) @ - dtcm enable
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orr r0, r0, #(1<<16) @ - dtcm enable
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orr r4, r4, #(1<<12) @ - instruction cache enable
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orr r0, r0, #(1<<12) @ - instruction cache enable
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orr r4, r4, #(1<<2) @ - data cache enable
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orr r0, r0, #(1<<2) @ - data cache enable
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orr r4, r4, #(1<<0) @ - mpu enable
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orr r0, r0, #(1<<0) @ - mpu enable
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mcr p15, 0, r4, c1, c0, 0 @ write control register
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Flush caches
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@ Flush caches
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mov r5, #0
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mov r0, #0
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mcr p15, 0, r5, c7, c5, 0 @ flush I-cache
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mcr p15, 0, r0, c7, c5, 0 @ flush I-cache
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mcr p15, 0, r5, c7, c6, 0 @ flush D-cache
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mcr p15, 0, r0, c7, c6, 0 @ flush D-cache
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mcr p15, 0, r5, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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@ Fixes mounting of SDMC
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@ Fixes mounting of SDMC
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ldr r0, =0x10000020
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ldr r0, =0x10000020
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@ -44,13 +44,13 @@ static inline void startChrono(u64 initialTicks)
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{
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{
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//Based on a NATIVE_FIRM disassembly
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//Based on a NATIVE_FIRM disassembly
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*(vu16 *)0x10003002 = 0; //67MHz
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REG_TIMER_CNT(0) = 0; //67MHz
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for(u32 i = 1; i < 4; i++) *(vu16 *)(0x10003002 + 4 * i) = 4; //Count-up
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for(u32 i = 1; i < 4; i++) REG_TIMER_CNT(i) = 4; //Count-up
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for(u32 i = 0; i < 4; i++) *(vu16 *)(0x10003000 + 4 * i) = (u16)(initialTicks >> (16 * i));
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for(u32 i = 0; i < 4; i++) REG_TIMER_VAL(i) = (u16)(initialTicks >> (16 * i));
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*(vu16 *)0x10003002 = 0x80; //67MHz; enabled
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REG_TIMER_CNT(0) = 0x80; //67MHz; enabled
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for(u32 i = 1; i < 4; i++) *(vu16 *)(0x10003002 + 4 * i) = 0x84; //Count-up; enabled
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for(u32 i = 1; i < 4; i++) REG_TIMER_CNT(i) = 0x84; //Count-up; enabled
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}
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}
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void chrono(u32 seconds)
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void chrono(u32 seconds)
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@ -64,7 +64,7 @@ void chrono(u32 seconds)
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do
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do
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{
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{
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res = 0;
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res = 0;
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for(u32 i = 0; i < 4; i++) res |= *(vu16 *)(0x10003000 + 4 * i) << (16 * i);
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for(u32 i = 0; i < 4; i++) res |= REG_TIMER_VAL(i) << (16 * i);
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}
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}
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while(res - startingTicks < seconds * TICKS_PER_SEC);
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while(res - startingTicks < seconds * TICKS_PER_SEC);
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@ -73,5 +73,5 @@ void chrono(u32 seconds)
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void stopChrono(void)
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void stopChrono(void)
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{
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{
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for(u32 i = 1; i < 4; i++) *(vu16 *)(0x10003002 + 4 * i) &= ~0x80;
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for(u32 i = 0; i < 4; i++) REG_TIMER_CNT(i) &= ~0x80;
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}
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}
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@ -10,6 +10,8 @@ u32 waitInput(void);
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void mcuReboot(void);
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void mcuReboot(void);
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#define TICKS_PER_SEC 67027964ULL
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#define TICKS_PER_SEC 67027964ULL
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#define REG_TIMER_CNT(i) *(vu16 *)(0x10003002 + 4 * i)
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#define REG_TIMER_VAL(i) *(vu16 *)(0x10003000 + 4 * i)
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void chrono(u32 seconds);
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void chrono(u32 seconds);
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void stopChrono(void);
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void stopChrono(void);
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