Adapt changes from b9s/next
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@@ -13,8 +13,8 @@ dir_build := build
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dir_out := ../$(dir_build)
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ASFLAGS := -mcpu=arm946e-s
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CFLAGS := -Wall -Wextra -mthumb $(ASFLAGS) -fno-builtin -std=c11 -Wno-main -O2 -flto -ffast-math
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LDFLAGS := -nostdlib
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CFLAGS := -Wall -Wextra -marm $(ASFLAGS) -fno-builtin -std=c11 -Wno-main -O2 -flto -ffast-math
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LDFLAGS := -nostartfiles -Wl,--nmagic
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objects = $(patsubst $(dir_source)/%.s, $(dir_build)/%.o, \
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$(patsubst $(dir_source)/%.c, $(dir_build)/%.o, \
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@@ -24,20 +24,15 @@
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#include "memory.h"
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#include "cache.h"
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void disableMpuAndJumpToEntrypoints(int argc, char **argv, void *arm11Entry, void *arm9Entry);
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void launchFirm(Firm *firm, int argc, char **argv)
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{
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//Copy FIRM sections to respective memory locations
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for(u32 sectionNum = 0; sectionNum < 4 && firm->section[sectionNum].size != 0; sectionNum++)
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memcpy(firm->section[sectionNum].address, (u8 *)firm + firm->section[sectionNum].offset, firm->section[sectionNum].size);
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//Ensure that all memory transfers have completed and that the caches have been flushed
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flushCaches();
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//Set ARM11 entrypoint
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*(vu32 *)0x1FFFFFFC = (u32)firm->arm11Entry;
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//Jump to ARM9 entrypoint. Also give it additional arguments it can dismiss
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((void (*)(int, char**, u32))firm->arm9Entry)(argc, argv, 0x0000BEEF);
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disableMpuAndJumpToEntrypoints(argc, argv, firm->arm9Entry, firm->arm11Entry);
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__builtin_unreachable();
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}
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@@ -24,17 +24,25 @@
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#include "cache.h"
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#include "firm.h"
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void main(int argc __attribute__((unused)), char **argv)
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void main(int argc, char **argv)
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{
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Firm *firm = (Firm *)0x24000000;
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Firm *firm = (Firm *)0x20001000;
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struct fb fbs[2];
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char absPath[24 + 255];
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if(argc == 2)
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{
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struct fb *fbsrc = (struct fb *)argv[1];
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fbs[0] = fbsrc[0];
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fbs[1] = fbsrc[1];
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}
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u32 i;
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for(i = 0; i < sizeof(absPath) - 1 && argv[0][i] != 0; i++)
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absPath[i] = argv[0][i];
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absPath[i] = 0;
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char *argvPassed[1] = {absPath};
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char *argvPassed[2] = {absPath, (char *)&fbs};
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launchFirm(firm, 1, argvPassed);
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launchFirm(firm, argc, argvPassed);
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}
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@@ -18,9 +18,40 @@
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@ reasonable legal notices or author attributions in that material or in the Appropriate Legal
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@ Notices displayed by works containing it.
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.arm
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.section .text.start
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.align 4
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.global _start
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_start:
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ldr sp, =0x27ffe000
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b main
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.text
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.balign 4
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.global disableMpuAndJumpToEntrypoints
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.type disableMpuAndJumpToEntrypoints, %function
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disableMpuAndJumpToEntrypoints:
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mov r4, r0
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mov r5, r1
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mov r6, r2
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mov r7, r3
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bl flushCaches
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@ Disable caches / MPU
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, #(1<<12) @ - instruction cache disable
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bic r0, #(1<<2) @ - data cache disable
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bic r0, #(1<<0) @ - mpu disable
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mcr p15, 0, r0, c1, c0, 0 @ write control register
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@ Set the ARM11 entrypoint
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mov r0, #0x20000000
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str r7, [r0, #-4]
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@ Jump to the ARM9 entrypoint
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mov r0, r4
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mov r1, r5
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ldr r2, =0xBEEF
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bx r6
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@@ -32,4 +32,10 @@ typedef uint64_t u64;
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typedef volatile u8 vu8;
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typedef volatile u16 vu16;
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typedef volatile u32 vu32;
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typedef volatile u64 vu64;
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typedef volatile u64 vu64;
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struct fb {
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u8 *top_left;
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u8 *top_right;
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u8 *bottom;
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} __attribute__((packed));
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