LowLevel/Luma3DS-3GX
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Move patches within emunand.c

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This commit is contained in:
Aurora
2016-05-25 15:26:51 +02:00
parent 9aeac7af92
commit c36fa01651
5 changed files with 35 additions and 35 deletions
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62
source/emunand.c
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@@ -40,6 +40,14 @@ void locateEmuNAND(u32 *off, u32 *head, u32 *emuNAND)
}
}
static inline void *getEmuCode(u8 *pos, u32 size)
{
const u8 pattern[] = {0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
//Looking for the last free space before Process9
return memsearch(pos + 0x13500, pattern, size - 0x13500, 6) + 0x455;
}
static inline u32 getSDMMC(u8 *pos, u32 size)
{
//Look for struct code
@@ -49,32 +57,39 @@ static inline u32 getSDMMC(u8 *pos, u32 size)
return *(u32 *)(off + 9) + *(u32 *)(off + 0xD);
}
static inline void getEmuRW(u8 *pos, u32 size, u16 **readOffset, u16 **writeOffset)
static inline void patchNANDRW(u8 *pos, u32 size, u32 branchOffset)
{
const u16 nandRedir[2] = {0x4C00, 0x47A0};
//Look for read/write code
const u8 pattern[] = {0x1E, 0x00, 0xC8, 0x05};
*readOffset = (u16 *)memsearch(pos, pattern, size, 4) - 3;
*writeOffset = (u16 *)memsearch((u8 *)(*readOffset + 5), pattern, 0x100, 4) - 3;
u16 *readOffset = (u16 *)memsearch(pos, pattern, size, 4) - 3;
u16 *writeOffset = (u16 *)memsearch((u8 *)(readOffset + 5), pattern, 0x100, 4) - 3;
*readOffset = nandRedir[0];
readOffset[1] = nandRedir[1];
((u32 *)readOffset)[1] = branchOffset;
*writeOffset = nandRedir[0];
writeOffset[1] = nandRedir[1];
((u32 *)writeOffset)[1] = branchOffset;
}
static inline u32 *getMPU(u8 *pos, u32 size)
static inline void patchMPU(u8 *pos, u32 size)
{
const u32 mpuPatch[3] = {0x00360003, 0x00200603, 0x001C0603};
//Look for MPU pattern
const u8 pattern[] = {0x03, 0x00, 0x24, 0x00};
return (u32 *)memsearch(pos, pattern, size, 4);
u32 *off = (u32 *)memsearch(pos, pattern, size, 4);
off[0] = mpuPatch[0];
off[6] = mpuPatch[1];
off[9] = mpuPatch[2];
}
static inline void *getEmuCode(u8 *pos, u32 size)
{
const u8 pattern[] = {0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00};
//Looking for the last free space before Process9
return memsearch(pos + 0x13500, pattern, size - 0x13500, 6) + 0x455;
}
void patchEmuNAND(u8 *arm9Section, u32 arm9SectionSize, u8 *process9Offset, u32 process9Size, u32 emuHeader, u32 branchAdditive)
void patchEmuNAND(u8 *arm9Section, u32 arm9SectionSize, u8 *process9Offset, u32 process9Size, u32 emuOffset, u32 emuHeader, u32 branchAdditive)
{
//Copy emuNAND code
void *emuCodeOffset = getEmuCode(arm9Section, arm9SectionSize);
@@ -91,24 +106,9 @@ void patchEmuNAND(u8 *arm9Section, u32 arm9SectionSize, u8 *process9Offset, u32
*pos_sdmmc = getSDMMC(process9Offset, process9Size);
//Add emuNAND hooks
u16 *emuRead,
*emuWrite;
u32 branchOffset = (u32)emuCodeOffset - branchAdditive;
getEmuRW(process9Offset, process9Size, &emuRead, &emuWrite);
const u16 nandRedir[2] = {0x4C00, 0x47A0};
*emuRead = nandRedir[0];
emuRead[1] = nandRedir[1];
((u32 *)emuRead)[1] = branchOffset;
*emuWrite = nandRedir[0];
emuWrite[1] = nandRedir[1];
((u32 *)emuWrite)[1] = branchOffset;
patchNANDRW(process9Offset, process9Size, branchOffset);
//Set MPU for emu code region
u32 *mpuOffset = getMPU(arm9Section, arm9SectionSize);
const u32 mpuPatch[3] = {0x00360003, 0x00200603, 0x001C0603};
*mpuOffset = mpuPatch[0];
mpuOffset[6] = mpuPatch[1];
mpuOffset[9] = mpuPatch[2];
patchMPU(arm9Section, arm9SectionSize);
}

2
source/emunand.h
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@@ -9,4 +9,4 @@
#define NCSD_MAGIC 0x4453434E
void locateEmuNAND(u32 *off, u32 *head, u32 *emuNAND);
void patchEmuNAND(u8 *arm9Section, u32 arm9SectionSize, u8 *process9Offset, u32 process9Size, u32 emuHeader, u32 branchAdditive);
void patchEmuNAND(u8 *arm9Section, u32 arm9SectionSize, u8 *process9Offset, u32 process9Size, u32 emuOffset, u32 emuHeader, u32 branchAdditive);

1
source/fatfs/diskio.c
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@@ -9,6 +9,7 @@
#include "diskio.h" /* FatFs lower layer API */
#include "sdmmc/sdmmc.h"
#include "../crypto.h"
/* Definitions of physical drive number for each media */
#define SDCARD 0

1
source/fatfs/sdmmc/common.h
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@@ -2,4 +2,3 @@
#include <stdbool.h>
#include "../../types.h"
#include "../../crypto.h"

2
source/firm.c
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@@ -291,7 +291,7 @@ static inline void patchNativeFirm(u32 nandType, u32 emuHeader, u32 a9lhMode)
if(nandType)
{
u32 branchAdditive = (u32)firm - section[2].offset + (u32)section[2].address;
patchEmuNAND(arm9Section, section[2].size, process9Offset, process9Size, emuHeader, branchAdditive);
patchEmuNAND(arm9Section, section[2].size, process9Offset, process9Size, emuOffset, emuHeader, branchAdditive);
}
//Apply FIRM0/1 writes patches on sysNAND to protect A9LH