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@ -47,6 +47,16 @@ void __attribute__((naked)) arm11Stub(void)
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((void (*)())*arm11Entry)();
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}
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/*
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About cache coherency:
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Flushing the data cache for **ALL** memory regions read from/written to by _both_ processors is mandatory on the arm9 processor.
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Thus, we make sure there'll be a cache miss on the arm9 next time it's read.
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Otherwise the arm9 won't see the changes made and things will break.
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On the arm11, in the environment we're in, the MMU isn't enabled and nothing is cached.
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*/
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static void invokeArm11Function(void (*func)())
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{
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static bool hasCopiedStub = false;
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@ -151,6 +161,7 @@ void clearScreens(bool clearTop, bool clearBottom)
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flushDCacheRange(&clearTopTmp, 1);
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flushDCacheRange(&clearBottomTmp, 1);
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flushDCacheRange((void *)fb, sizeof(struct fb));
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invokeArm11Function(ARM11);
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}
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@ -257,6 +268,7 @@ void initScreens(void)
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if(PDN_GPU_CNT == 1)
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{
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flushDCacheRange(&configData, sizeof(CfgData));
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flushDCacheRange((void *)fb, sizeof(struct fb));
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invokeArm11Function(ARM11);
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clearScreens(true, true);
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@ -269,4 +281,4 @@ void initScreens(void)
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clearScreens(true, true);
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updateBrightness(MULTICONFIG(BRIGHTNESS));
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}
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}
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}
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