Backport FIRM whitelist from b9s
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692a94fe5e
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8e22080e05
@ -409,13 +409,20 @@ u32 patch1x2xNativeAndSafeFirm(bool enableExceptionHandlers)
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static __attribute__((noinline)) bool overlaps(u32 as, u32 ae, u32 bs, u32 be)
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{
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if (as <= bs && bs <= ae)
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if(as <= bs && bs <= ae)
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return true;
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else if (bs <= as && as <= be)
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if(bs <= as && as <= be)
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return true;
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return false;
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}
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static __attribute__((noinline)) bool inRange(u32 as, u32 ae, u32 bs, u32 be)
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{
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if(as >= bs && ae <= be)
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return true;
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return false;
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}
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bool checkFirmPayload(void)
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{
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if(memcmp(firm->magic, "FIRM", 4) != 0 || firm->arm9Entry == NULL) //Allow for the ARM11 entrypoint to be zero in which case nothing is done on the ARM11 side
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@ -441,9 +448,11 @@ bool checkFirmPayload(void)
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if((section->offset < 0x200) ||
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(section->address + section->size < section->address) || //Overflow check
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((u32)section->address & 3) || (section->offset & 0x1FF) || (section->size & 0x1FF) || //Alignment check
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(overlaps((u32)section->address, (u32)section->address + section->size, 0x01FF8000, 0x01FF8000 + 0x8000)) ||
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(overlaps((u32)section->address, (u32)section->address + section->size, 0x1FFFFC00, 0x20000000)) ||
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(overlaps((u32)section->address, (u32)section->address + section->size, (u32)firm + section->offset, (u32)firm + size)))
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(overlaps((u32)section->address, (u32)section->address + section->size, (u32)firm + section->offset, (u32)firm + size)) ||
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((!inRange((u32)section->address, (u32)section->address + section->size, 0x08000000, 0x08000000 + 0x00100000)) &&
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(!inRange((u32)section->address, (u32)section->address + section->size, 0x18000000, 0x18000000 + 0x00600000)) &&
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(!inRange((u32)section->address, (u32)section->address + section->size, 0x1FF00000, 0x1FFFFC00)) &&
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(!inRange((u32)section->address, (u32)section->address + section->size, 0x20000000, 0x20000000 + 0x8000000))))
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return false;
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sha(hash, (u8 *)firm + section->offset, section->size, SHA_256_MODE);
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@ -58,11 +58,11 @@ _start:
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@ Set MPU permissions and cache settings
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ldr r0, =0xFFFF001D @ ffff0000 32k | bootrom (unprotected part)
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ldr r1, =0xFFF0001B @ fff00000 16k | dtcm
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ldr r1, =0xFFF0801B @ fff00000 16k | dtcm
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ldr r2, =0x01FF801D @ 01ff8000 32k | itcm
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ldr r3, =0x08000029 @ 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r3, =0x08000027 @ 08000000 1M | arm9 mem
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ldr r4, =0x10000029 @ 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r5, =0x20000037 @ 20000000 256M | fcram (O3DS / N3DS)
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ldr r5, =0x20000035 @ 20000000 128M | fcram
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ldr r6, =0x1FF00027 @ 1FF00000 1M | dsp / axi wram
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ldr r7, =0x1800002D @ 18000000 8M | vram (+ 2MB)
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mov r8, #0x29
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