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Refactor fatalExceptionHandlers.s a bit

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This commit is contained in:
TuxSH 2017-06-07 23:58:29 +02:00
parent a16d1ebe33
commit 84d736c2eb
2 changed files with 14 additions and 11 deletions
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23
sysmodules/rosalina/kernel_extension/source/fatalExceptionHandlers.s
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@ -78,18 +78,21 @@ _commonHandler:
cpsid aif cpsid aif
push {r0} push {r0}
ldr r0, =_fatalExceptionOccured ldr r0, =fatalExceptionOccured
ldr r0, [r0] ldr r0, [r0]
cmp r0, #0 cmp r0, #0
bne _die_loop bne _die_loop
pop {r0} pop {r0}
ldr r9, =_regs ldr r9, =exceptionStackTop
ldr r9, [r9]
sub r9, #0x400
add r9, #4
stmia r9, {r0-r7} stmia r9, {r0-r7}
mov r1, r8 mov r1, r8
pop {r8,r9} pop {r8,r9}
ldr r0, =_fatalExceptionOccured ldr r0, =fatalExceptionOccured
mov r4, #1 mov r4, #1
_try_lock: _try_lock:
@ -108,8 +111,10 @@ _commonHandler:
mrs r2, spsr mrs r2, spsr
mrs r3, cpsr mrs r3, cpsr
ldr r6, =_regs ldr r6, =exceptionStackTop
add r6, #0x20 ldr r6, [r6]
sub r6, #(0x400 - 0x20)
add r6, #4
ands r4, r2, #0xf @ get the mode that triggered the exception ands r4, r2, #0xf @ get the mode that triggered the exception
moveq r4, #0xf @ usr => sys moveq r4, #0xf @ usr => sys
@ -166,7 +171,8 @@ _commonHandler:
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c10, 5 @ Drain Memory Barrier mcr p15, 0, r0, c7, c10, 5 @ Drain Memory Barrier
ldr r0, =_regs sub r0, sp, #(0x400 - 0x100)
add r0, #4
mrc p15, 0, r2, c0, c0, 5 @ CPU ID register mrc p15, 0, r2, c0, c0, 5 @ CPU ID register
bl fatalExceptionHandlersMain bl fatalExceptionHandlersMain
@ -244,8 +250,3 @@ dataAbortHandler:
subs pc, lr, #4 subs pc, lr, #4
GEN_USUAL_HANDLER _dataAbortNormal, 3, 16 GEN_USUAL_HANDLER _dataAbortNormal, 3, 16
.bss
.balign 4
_regs: .skip (4 * 23)
_fatalExceptionOccured: .word 0

2
sysmodules/rosalina/kernel_extension/source/fatalExceptionHandlersMain.c
View File

@ -33,6 +33,8 @@
#define REG_DUMP_SIZE 4 * 23 #define REG_DUMP_SIZE 4 * 23
#define CODE_DUMP_SIZE 48 #define CODE_DUMP_SIZE 48
bool fatalExceptionOccured = false;
bool isExceptionFatal(u32 spsr, u32 *regs, u32 index) bool isExceptionFatal(u32 spsr, u32 *regs, u32 index)
{ {
if((spsr & 0x1f) != 0x10) return true; if((spsr & 0x1f) != 0x10) return true;