LowLevel/Luma3DS-3GX
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Changed payload offset, added clearScreen function, etc.

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This commit is contained in:
Reisyukaku
2015-08-06 01:17:10 -04:00
parent afbdf20d28
commit 4f3761d4a5
12 changed files with 44 additions and 22 deletions
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7
source/draw.c
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@@ -6,6 +6,13 @@
#include "draw.h"
#include "fs.h"
void clearScreen(void){
memset(fb->top_left, 0, 0x38400);
memset(fb->top_right, 0, 0x38400);
memset(fb->bottom, 0, 0x38400);
}
void loadSplash(void){
clearScreen();
fileRead(fb->top_left, "/rei/splash.bin", 0x46500);
}

1
source/draw.h
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@@ -11,4 +11,5 @@ static struct fb {
u8 *bottom;
} *fb = (struct fb *)0x23FFFE00;
void clearScreen(void);
void loadSplash(void);

34
source/firm.c
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@@ -53,17 +53,18 @@ void patchFirm(void){
void launchFirm(void){
//Set MPU
__asm__ (
"msr cpsr_c, #0xDF\n\t"
"ldr r0, =0x10000035\n\t"
"ldr r4, =0x18000035\n\t"
"mcr p15, 0, r0, c6, c3, 0\n\t"
"mcr p15, 0, r4, c6, c4, 0\n\t"
"mrc p15, 0, r0, c2, c0, 0\n\t"
"mrc p15, 0, r4, c2, c0, 1\n\t"
"mrc p15, 0, r1, c3, c0, 0\n\t"
"mrc p15, 0, r2, c5, c0, 2\n\t"
"mrc p15, 0, r3, c5, c0, 3\n\t"
__asm__ (
"msr cpsr_c, #0xDF\n\t" //Set system mode, disable interrupts
"ldr r0, =0x10000035\n\t" //Memory area 0x10000000-0x18000000, enabled, 128MB
"ldr r4, =0x18000035\n\t" //Memory area 0x18000000-0x20000000, enabled, 128MB
"mcr p15, 0, r0, c6, c3, 0\n\t" //Set memory area 3 (0x10000000-0x18000000)
"mcr p15, 0, r4, c6, c4, 0\n\t" //Set memory area 4 (0x18000000-0x20000000)
"mrc p15, 0, r0, c2, c0, 0\n\t" //read data cacheable bit
"mrc p15, 0, r4, c2, c0, 1\n\t" //read inst cacheable bit
"mrc p15, 0, r1, c3, c0, 0\n\t" //read data writeable
"mrc p15, 0, r2, c5, c0, 2\n\t" //read data access permission
"mrc p15, 0, r3, c5, c0, 3\n\t" //read inst access permission
"orr r0, r0, #0x30\n\t"
"orr r4, r4, #0x30\n\t"
"orr r1, r1, #0x30\n\t"
@@ -71,13 +72,14 @@ void launchFirm(void){
"bic r3, r3, #0xF0000\n\t"
"orr r2, r2, #0x30000\n\t"
"orr r3, r3, #0x30000\n\t"
"mcr p15, 0, r0, c2, c0, 0\n\t"
"mcr p15, 0, r4, c2, c0, 1\n\t"
"mcr p15, 0, r1, c3, c0, 0\n\t"
"mcr p15, 0, r2, c5, c0, 2\n\t"
"mcr p15, 0, r3, c5, c0, 3\n\t"
"mcr p15, 0, r0, c2, c0, 0\n\t" //write data cacheable bit
"mcr p15, 0, r4, c2, c0, 1\n\t" //write inst cacheable bit
"mcr p15, 0, r1, c3, c0, 0\n\t" //write data writeable
"mcr p15, 0, r2, c5, c0, 2\n\t" //write data access permission
"mcr p15, 0, r3, c5, c0, 3\n\t" //write inst access permission
::: "r0", "r1", "r2", "r3", "r4"
);
//Copy firm partitions to respective memory locations
memcpy(section[0].address, (u8*)firmLocation + section[0].offset, section[0].size);
memcpy(section[1].address, (u8*)firmLocation + section[1].offset, section[1].size);

2
source/patches.h
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@@ -56,7 +56,7 @@ u32 threadCode = KERNEL9 + (0x0801A6E0 - K9_ADDR);
u32 threadHook1 = PROC9 + (0x080860B0 - P9_ADDR);
u32 threadHook2 = PROC9 + (0x080860E4 - P9_ADDR);
//Patches
u8 th1[4] = {0x2C, 0xF0, 0x9F, 0xE5};
u8 th1[4] = {0x2C, 0xF0, 0x9F, 0xE5}; //ldr pc, =0x080860E4
u8 th2[4] = {0xE0, 0xA6, 0x01, 0x08};
#endif