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Disable interrupts and do some refactoring.

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TuxSH
2016-08-13 20:49:40 +02:00
parent 905777466d
commit 457b4cec13
4 changed files with 31 additions and 19 deletions
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33
patches/reboot.s
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@@ -41,26 +41,29 @@ payload_maxsize equ 0x10000 ; Maximum size for the payload (maximum that CakeB
read_payload: read_payload:
; Read file ; Read file
mov r0, r7 mov r0, r7
adr r1, bytes_read adr r1, bytes_read
ldr r2, =payload_addr ldr r2, =payload_addr
cmp r4, #0 cmp r4, #0
movne r3, #0x12000 ; Skip the first 0x12000 bytes. movne r3, #0x12000 ; Skip the first 0x12000 bytes.
moveq r3, payload_maxsize moveq r3, payload_maxsize
ldr r6, [sp, #0x3A8-0x198] ldr r6, [sp, #0x3A8-0x198]
ldr r6, [r6, #0x28] ldr r6, [r6, #0x28]
blx r6 blx r6
cmp r4, #0 cmp r4, #0
movne r4, #0 movne r4, #0
bne read_payload ; Go read the real payload. bne read_payload ; Go read the real payload.
; Copy the last digits of the wanted firm to the 5th byte of the payload ; Copy the low TID (in UTF-16) of the wanted firm to the 5th byte of the payload
add r2, sp, #0x3A8 - 0x70 add r0, sp, #0x3A8 - 0x70
ldr r0, [r2, #0x27] add r0, 0x1A
ldr r1, =payload_addr + 4 add r1, r0, #0x10
str r0, [r1] ldr r2, =payload_addr + 4
ldr r0, [r2, #0x2B] copy_TID_low:
str r0, [r1, #4] ldrh r3, [r0], #2
strh r3, [r2], #2
cmp r0, r1
blo copy_TID_low
; Set kernel state ; Set kernel state
mov r0, #0 mov r0, #0
@@ -81,10 +84,10 @@ payload_maxsize equ 0x10000 ; Maximum size for the payload (maximum that CakeB
bytes_read: .word 0 bytes_read: .word 0
fopen: .ascii "OPEN" fopen: .ascii "OPEN"
.pool .pool
bin_fname: .dcw "sdmc:/arm9loaderhax.bin" bin_fname: .dcw "sdmc:/arm9loaderhax.bin"
.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 .word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
dat_fname: .dcw "sdmc:/Luma3DS.dat" dat_fname: .dcw "sdmc:/Luma3DS.dat"
.word 0 .word 0
.align 4 .align 4
kernelcode_start: kernelcode_start:

6
source/firm.c
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@@ -36,6 +36,8 @@
#include "i2c.h" #include "i2c.h"
#include "../build/injector.h" #include "../build/injector.h"
extern u16 launchedFirmTIDLow[8]; //defined in start.s
static firmHeader *const firm = (firmHeader *)0x24000000; static firmHeader *const firm = (firmHeader *)0x24000000;
static const firmSectionHeader *section; static const firmSectionHeader *section;
@@ -76,14 +78,14 @@ void main(void)
needConfig = fileRead(&config, configPath) ? MODIFY_CONFIGURATION : CREATE_CONFIGURATION; needConfig = fileRead(&config, configPath) ? MODIFY_CONFIGURATION : CREATE_CONFIGURATION;
//Determine if this is a firmlaunch boot //Determine if this is a firmlaunch boot
if(*(vu8 *)0x23F00005) if(launchedFirmTIDLow[5] != 0)
{ {
if(needConfig == CREATE_CONFIGURATION) mcuReboot(); if(needConfig == CREATE_CONFIGURATION) mcuReboot();
isFirmlaunch = true; isFirmlaunch = true;
//'0' = NATIVE_FIRM, '1' = TWL_FIRM, '2' = AGB_FIRM //'0' = NATIVE_FIRM, '1' = TWL_FIRM, '2' = AGB_FIRM
firmType = *(vu8 *)0x23F00009 == '3' ? SAFE_FIRM : (FirmwareType)(*(vu8 *)0x23F00005 - '0'); firmType = launchedFirmTIDLow[7] == u'3' ? SAFE_FIRM : (FirmwareType)(launchedFirmTIDLow[5] - u'0');
nandType = (FirmwareSource)BOOTCONFIG(0, 3); nandType = (FirmwareSource)BOOTCONFIG(0, 3);
firmSource = (FirmwareSource)BOOTCONFIG(2, 1); firmSource = (FirmwareSource)BOOTCONFIG(2, 1);

2
source/firm.h
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@@ -53,7 +53,7 @@ typedef enum ConfigurationStatus
MODIFY_CONFIGURATION = 1, MODIFY_CONFIGURATION = 1,
CREATE_CONFIGURATION = 2 CREATE_CONFIGURATION = 2
} ConfigurationStatus; } ConfigurationStatus;
static inline u32 loadFirm(FirmwareType firmType); static inline u32 loadFirm(FirmwareType firmType);
static inline void patchNativeFirm(u32 firmVersion, FirmwareSource nandType, u32 emuHeader, bool isA9lh); static inline void patchNativeFirm(u32 firmVersion, FirmwareSource nandType, u32 emuHeader, bool isA9lh);
static inline void patchLegacyFirm(FirmwareType firmType); static inline void patchLegacyFirm(FirmwareType firmType);

9
source/start.s
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@@ -26,12 +26,19 @@
_start: _start:
b start b start
.word 0, 0 .global launchedFirmTIDLow
launchedFirmTIDLow:
.hword 0, 0, 0, 0, 0, 0, 0, 0
start: start:
@ Change the stack pointer @ Change the stack pointer
mov sp, #0x27000000 mov sp, #0x27000000
@ Disable interrupts
mrs r0, cpsr
orr r0, #0x1C0
msr cpsr_cx, r0
@ Disable caches / MPU @ Disable caches / MPU
mrc p15, 0, r0, c1, c0, 0 @ read control register mrc p15, 0, r0, c1, c0, 0 @ read control register
bic r0, #(1<<12) @ - instruction cache disable bic r0, #(1<<12) @ - instruction cache disable