Merged my changes
There you have it!
This commit is contained in:
Aurora
159
reboot/rebootCode.s
Normal file
159
reboot/rebootCode.s
Normal file
@@ -0,0 +1,159 @@
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.nds
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firm_size equ 0x000EA000
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firm_addr equ 0x24000000
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fopen equ 0x08059D10
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fread equ 0x0804CC54
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pxi_wait_recv equ 0x08054134
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.macro svc, num
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.if isArm()
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.word 0xEF000000 | num
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.else
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.if num > 0xFF
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.error "bitch you crazu"
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.endif
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.halfword 0xDF00 | num
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.endif
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.endmacro
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.create "reboot1.bin", 0x080849DC
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.org 0x080849DC
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.arm
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patch005:
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ldr r0, =0x2000E000
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mov r1, #0x200
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mov r2, #0
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add r1, r1, r0
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@@memset_loop:
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str r2, [r0]
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add r0, r0, #4
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cmp r0, r1
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blt @@memset_loop
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ldr r0, =0x2000E000
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ldr r1, =firm_fname
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mov r2, #1
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blx fopen
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ldr r0, =0x2000E000
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ldr r1, =0x2000E100
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mov r2, #firm_addr
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mov r3, #firm_size
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blx fread
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ldr r4, =0x44846
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blx pxi_wait_recv
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cmp r0, r4
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bne patch005
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mov r2, #0
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mov r3, r2
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mov r1, r2
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mov r0, r2
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svc 0x7C
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ldr r0, =0x80FF4FC
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svc 0x7B
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@@inf_loop:
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b @@inf_loop
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.pool
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firm_fname:
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.close
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.create "reboot2.bin", 0x080933CC
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.org 0x080933CC
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.arm
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stmfd sp!, {r4-r11,lr}
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sub sp, sp, #0x3C
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mrc p15, 0, r0, c2, c0, 0 ; dcacheable
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mrc p15, 0, r12, c2, c0, 1 ; icacheable
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mrc p15, 0, r1, c3, c0, 0 ; write bufferable
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mrc p15, 0, r2, c5, c0, 2 ; daccess
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mrc p15, 0, r3, c5, c0, 3 ; iaccess
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ldr r4, =0x18000035 ; 0x18000000 128M
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bic r2, r2, #0xF0000 ; unprotect region 4
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bic r3, r3, #0xF0000 ; unprotect region 4
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orr r0, r0, #0x10 ; dcacheable region 4
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orr r2, r2, #0x30000 ; region 4 r/w
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orr r3, r3, #0x30000 ; region 4 r/w
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orr r12, r12, #0x10 ; icacheable region 4
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orr r1, r1, #0x10 ; write bufferable region 4
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mcr p15, 0, r0, c2, c0, 0
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mcr p15, 0, r12, c2, c0, 1
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mcr p15, 0, r1, c3, c0, 0 ; write bufferable
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mcr p15, 0, r2, c5, c0, 2 ; daccess
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mcr p15, 0, r3, c5, c0, 3 ; iaccess
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mcr p15, 0, r4, c6, c4, 0 ; region 4 (hmmm)
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mrc p15, 0, r0, c2, c0, 0 ; dcacheable
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mrc p15, 0, r1, c2, c0, 1 ; icacheable
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mrc p15, 0, r2, c3, c0, 0 ; write bufferable
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orr r0, r0, #0x20 ; dcacheable region 5
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orr r1, r1, #0x20 ; icacheable region 5
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orr r2, r2, #0x20 ; write bufferable region 5
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mcr p15, 0, r0, c2, c0, 0 ; dcacheable
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mcr p15, 0, r1, c2, c0, 1 ; icacheable
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mcr p15, 0, r2, c3, c0, 0 ; write bufferable
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mov r4, #firm_addr
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add r3, r4, #0x40
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ldr r0, [r3] ; offset
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add r0, r0, r4 ; src
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ldr r1, [r3,#4] ; dst
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ldr r2, [r3,#8] ; size
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bl memcpy32
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add r3, r4, #0x70
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ldr r0, [r3]
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add r0, r0, r4 ; src
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ldr r1, [r3,#4] ; dst
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ldr r2, [r3,#8] ; size
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bl memcpy32
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add r3, r4, #0xA0
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ldr r0, [r3]
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add r0, r0, r4 ; src
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ldr r1, [r3,#4] ; dst
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ldr r2, [r3,#8] ; size
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bl memcpy32
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mov r2, #0
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mov r1, r2
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@flush_cache:
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mov r0, #0
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mov r3, r2, lsl#30
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@flush_cache_inner_loop:
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orr r12, r3, r0, lsl#5
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mcr p15, 0, r1, c7, c10, 4 ; drain write buffer
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mcr p15, 0, r12, c7, c14, 2 ; clean and flush dcache entry (index and segment)
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add r0, r0, #1
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cmp r0, #0x20
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bcc @flush_cache_inner_loop
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add r2, r2, #1
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cmp r2, #4
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bcc @flush_cache
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mcr p15, 0, r1, c7, c10, 4 ; drain write buffer
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@mpu_enable:
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ldr r0, =0x42078 ; alt vector select, enable itcm
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r1, c7, c5, 0 ; flush dcache
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mcr p15, 0, r1, c7, c6, 0 ; flush icache
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mcr p15, 0, r1, c7, c10, 4 ; drain write buffer
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mov r0, #firm_addr
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mov r1, 0X1FFFFFFC
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ldr r2, [r0,#8] ; arm11 entry
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str r2, [r1]
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ldr r0, [r0,#0xC] ; arm9 entry
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add sp, sp, #0x3C
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ldmfd sp!, {r4-r11,lr}
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bx r0
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.pool
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memcpy32: ; memcpy32(void *src, void *dst, unsigned int size)
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mov r12, lr
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stmfd sp!, {r0-r4}
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add r2, r2, r0
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@memcpy_loop:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r0, r2
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blt @memcpy_loop
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ldmfd sp!, {r0-r4}
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mov lr, r12
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bx lr
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.pool
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.close
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159
reboot/rebootCodeNtr.s
Normal file
159
reboot/rebootCodeNtr.s
Normal file
@@ -0,0 +1,159 @@
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.nds
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firm_size equ 0x000EB000
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firm_addr equ 0x24000000
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fopen equ 0x0805B180
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fread equ 0x0804D9B0
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pxi_wait_recv equ 0x08055178
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.macro svc, num
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.if isArm()
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.word 0xEF000000 | num
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.else
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.if num > 0xFF
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.error "bitch you crazu"
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.endif
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.halfword 0xDF00 | num
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.endif
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.endmacro
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.create "reboot1.bin", 0x080859C8
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.org 0x080859C8
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.arm
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patch005:
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ldr r0, =0x2000E000
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mov r1, #0x200
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mov r2, #0
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add r1, r1, r0
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@@memset_loop:
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str r2, [r0]
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add r0, r0, #4
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cmp r0, r1
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blt @@memset_loop
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ldr r0, =0x2000E000
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ldr r1, =firm_fname
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mov r2, #1
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blx fopen
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ldr r0, =0x2000E000
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ldr r1, =0x2000E100
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mov r2, #firm_addr
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mov r3, #firm_size
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blx fread
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ldr r4, =0x44846
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blx pxi_wait_recv
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cmp r0, r4
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bne patch005
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mov r2, #0
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mov r3, r2
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mov r1, r2
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mov r0, r2
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svc 0x7C
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ldr r0, =0x80FF4FC
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svc 0x7B
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@@inf_loop:
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b @@inf_loop
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.pool
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firm_fname:
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.close
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.create "reboot2.bin", 0x08094454
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.org 0x08094454
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.arm
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stmfd sp!, {r4-r11,lr}
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sub sp, sp, #0x3C
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mrc p15, 0, r0, c2, c0, 0 ; dcacheable
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mrc p15, 0, r12, c2, c0, 1 ; icacheable
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mrc p15, 0, r1, c3, c0, 0 ; write bufferable
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mrc p15, 0, r2, c5, c0, 2 ; daccess
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mrc p15, 0, r3, c5, c0, 3 ; iaccess
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ldr r4, =0x18000035 ; 0x18000000 128M
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bic r2, r2, #0xF0000 ; unprotect region 4
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bic r3, r3, #0xF0000 ; unprotect region 4
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orr r0, r0, #0x10 ; dcacheable region 4
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orr r2, r2, #0x30000 ; region 4 r/w
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orr r3, r3, #0x30000 ; region 4 r/w
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orr r12, r12, #0x10 ; icacheable region 4
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orr r1, r1, #0x10 ; write bufferable region 4
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mcr p15, 0, r0, c2, c0, 0
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mcr p15, 0, r12, c2, c0, 1
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mcr p15, 0, r1, c3, c0, 0 ; write bufferable
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mcr p15, 0, r2, c5, c0, 2 ; daccess
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mcr p15, 0, r3, c5, c0, 3 ; iaccess
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mcr p15, 0, r4, c6, c4, 0 ; region 4 (hmmm)
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mrc p15, 0, r0, c2, c0, 0 ; dcacheable
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mrc p15, 0, r1, c2, c0, 1 ; icacheable
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mrc p15, 0, r2, c3, c0, 0 ; write bufferable
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orr r0, r0, #0x20 ; dcacheable region 5
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orr r1, r1, #0x20 ; icacheable region 5
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orr r2, r2, #0x20 ; write bufferable region 5
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mcr p15, 0, r0, c2, c0, 0 ; dcacheable
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mcr p15, 0, r1, c2, c0, 1 ; icacheable
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mcr p15, 0, r2, c3, c0, 0 ; write bufferable
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mov r4, #firm_addr
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add r3, r4, #0x40
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ldr r0, [r3] ; offset
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add r0, r0, r4 ; src
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ldr r1, [r3,#4] ; dst
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ldr r2, [r3,#8] ; size
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bl memcpy32
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add r3, r4, #0x70
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ldr r0, [r3]
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add r0, r0, r4 ; src
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ldr r1, [r3,#4] ; dst
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ldr r2, [r3,#8] ; size
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bl memcpy32
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add r3, r4, #0xA0
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ldr r0, [r3]
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add r0, r0, r4 ; src
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ldr r1, [r3,#4] ; dst
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ldr r2, [r3,#8] ; size
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bl memcpy32
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mov r2, #0
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mov r1, r2
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@flush_cache:
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mov r0, #0
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mov r3, r2, lsl#30
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@flush_cache_inner_loop:
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orr r12, r3, r0, lsl#5
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mcr p15, 0, r1, c7, c10, 4 ; drain write buffer
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mcr p15, 0, r12, c7, c14, 2 ; clean and flush dcache entry (index and segment)
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add r0, r0, #1
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cmp r0, #0x20
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bcc @flush_cache_inner_loop
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add r2, r2, #1
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cmp r2, #4
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bcc @flush_cache
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mcr p15, 0, r1, c7, c10, 4 ; drain write buffer
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@mpu_enable:
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ldr r0, =0x42078 ; alt vector select, enable itcm
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mcr p15, 0, r0, c1, c0, 0
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mcr p15, 0, r1, c7, c5, 0 ; flush dcache
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mcr p15, 0, r1, c7, c6, 0 ; flush icache
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mcr p15, 0, r1, c7, c10, 4 ; drain write buffer
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mov r0, #firm_addr
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mov r1, 0X1FFFFFFC
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ldr r2, [r0,#8] ; arm11 entry
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str r2, [r1]
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ldr r0, [r0,#0xC] ; arm9 entry
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add sp, sp, #0x3C
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ldmfd sp!, {r4-r11,lr}
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bx r0
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.pool
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memcpy32: ; memcpy32(void *src, void *dst, unsigned int size)
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mov r12, lr
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stmfd sp!, {r0-r4}
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add r2, r2, r0
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@memcpy_loop:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r0, r2
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blt @memcpy_loop
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ldmfd sp!, {r0-r4}
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mov lr, r12
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bx lr
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.pool
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.close
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