From 42885560ede8527b7f1325f78604916db225227e Mon Sep 17 00:00:00 2001 From: Aurora Date: Sun, 13 Mar 2016 16:48:57 +0100 Subject: [PATCH] Some clean-up --- source/crypto.c | 8 ++++---- source/crypto.h | 52 ++++++++++++++++++++++++------------------------- source/firm.c | 12 ++++++------ source/firm.h | 7 +++++-- 4 files changed, 41 insertions(+), 38 deletions(-) diff --git a/source/crypto.c b/source/crypto.c index 972f51c..0bb6fdc 100755 --- a/source/crypto.c +++ b/source/crypto.c @@ -54,10 +54,10 @@ __asm__\ } #endif /*__thumb__*/ -static void aes_setkey(u8 keyslot, const void* key, u32 keyType, u32 mode) +static void aes_setkey(u8 keyslot, const void *key, u32 keyType, u32 mode) { if(keyslot <= 0x03) return; // Ignore TWL keys for now - u32 * key32 = (u32 *)key; + u32 *key32 = (u32 *)key; *REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode; *REG_AESKEYCNT = (*REG_AESKEYCNT >> 6 << 6) | keyslot | AES_KEYCNT_WRITE; @@ -76,7 +76,7 @@ static void aes_use_keyslot(u8 keyslot) *REG_AESCNT = *REG_AESCNT | 0x04000000; /* mystery bit */ } -static void aes_setiv(const void* iv, u32 mode) +static void aes_setiv(const void *iv, u32 mode) { const u32 *iv32 = (const u32 *)iv; *REG_AESCNT = (*REG_AESCNT & ~(AES_CNT_INPUT_ENDIAN | AES_CNT_INPUT_ORDER)) | mode; @@ -100,7 +100,7 @@ static void aes_setiv(const void* iv, u32 mode) static void aes_advctr(void *ctr, u32 val, u32 mode) { - u32 *ctr32 = (u32*)ctr; + u32 *ctr32 = (u32 *)ctr; int i; if(mode & AES_INPUT_BE) diff --git a/source/crypto.h b/source/crypto.h index cd671a6..e8b547c 100755 --- a/source/crypto.h +++ b/source/crypto.h @@ -5,47 +5,47 @@ #include "types.h" /**************************AES****************************/ -#define REG_AESCNT ((volatile u32*)0x10009000) -#define REG_AESBLKCNT ((volatile u32*)0x10009004) -#define REG_AESWRFIFO ((volatile u32*)0x10009008) -#define REG_AESRDFIFO ((volatile u32*)0x1000900C) -#define REG_AESKEYSEL ((volatile u8 *)0x10009010) -#define REG_AESKEYCNT ((volatile u8 *)0x10009011) -#define REG_AESCTR ((volatile u32*)0x10009020) +#define REG_AESCNT ((vu32 *)0x10009000) +#define REG_AESBLKCNT ((vu32 *)0x10009004) +#define REG_AESWRFIFO ((vu32 *)0x10009008) +#define REG_AESRDFIFO ((vu32 *)0x1000900C) +#define REG_AESKEYSEL ((vu8 *)0x10009010) +#define REG_AESKEYCNT ((vu8 *)0x10009011) +#define REG_AESCTR ((vu32 *)0x10009020) -#define REG_AESKEYFIFO ((volatile u32*)0x10009100) -#define REG_AESKEYXFIFO ((volatile u32*)0x10009104) -#define REG_AESKEYYFIFO ((volatile u32*)0x10009108) +#define REG_AESKEYFIFO ((vu32 *)0x10009100) +#define REG_AESKEYXFIFO ((vu32 *)0x10009104) +#define REG_AESKEYYFIFO ((vu32 *)0x10009108) #define AES_CCM_DECRYPT_MODE (0u << 27) #define AES_CCM_ENCRYPT_MODE (1u << 27) -#define AES_CTR_MODE (2u << 27) -#define AES_CTR_MODE (2u << 27) +#define AES_CTR_MODE (2u << 27) +#define AES_CTR_MODE (2u << 27) #define AES_CBC_DECRYPT_MODE (4u << 27) #define AES_CBC_ENCRYPT_MODE (5u << 27) #define AES_ECB_DECRYPT_MODE (6u << 27) #define AES_ECB_ENCRYPT_MODE (7u << 27) -#define AES_ALL_MODES (7u << 27) +#define AES_ALL_MODES (7u << 27) -#define AES_CNT_START 0x80000000 -#define AES_CNT_INPUT_ORDER 0x02000000 +#define AES_CNT_START 0x80000000 +#define AES_CNT_INPUT_ORDER 0x02000000 #define AES_CNT_OUTPUT_ORDER 0x01000000 #define AES_CNT_INPUT_ENDIAN 0x00800000 #define AES_CNT_OUTPUT_ENDIAN 0x00400000 -#define AES_CNT_FLUSH_READ 0x00000800 -#define AES_CNT_FLUSH_WRITE 0x00000400 +#define AES_CNT_FLUSH_READ 0x00000800 +#define AES_CNT_FLUSH_WRITE 0x00000400 -#define AES_INPUT_BE (AES_CNT_INPUT_ENDIAN) -#define AES_INPUT_LE 0 -#define AES_INPUT_NORMAL (AES_CNT_INPUT_ORDER) -#define AES_INPUT_REVERSED 0 +#define AES_INPUT_BE (AES_CNT_INPUT_ENDIAN) +#define AES_INPUT_LE 0 +#define AES_INPUT_NORMAL (AES_CNT_INPUT_ORDER) +#define AES_INPUT_REVERSED 0 -#define AES_BLOCK_SIZE 0x10 +#define AES_BLOCK_SIZE 0x10 -#define AES_KEYCNT_WRITE (1 << 0x7) -#define AES_KEYNORMAL 0 -#define AES_KEYX 1 -#define AES_KEYY 2 +#define AES_KEYCNT_WRITE (1 << 0x7) +#define AES_KEYNORMAL 0 +#define AES_KEYX 1 +#define AES_KEYY 2 //NAND/FIRM stuff void nandFirm0(u8 *outbuf, u32 size, u32 console); diff --git a/source/firm.c b/source/firm.c index 66ee511..ff1f863 100755 --- a/source/firm.c +++ b/source/firm.c @@ -27,10 +27,10 @@ static const char *firmPathPatched = NULL; void setupCFW(void){ - //Determine if booting with A9LH via PDN_SPI_CNT - u32 a9lhBoot = (*(u8 *)0x101401C0 == 0x0) ? 1 : 0; - //Retrieve the last booted FIRM via CFG_BOOTENV - u8 previousFirm = *(u8 *)0x10010000; + //Determine if booting with A9LH + u32 a9lhBoot = (PDN_SPI_CNT == 0x0) ? 1 : 0; + //Retrieve the last booted FIRM + u8 previousFirm = CFG_BOOTENV; u32 overrideConfig = 0; const char lastConfigPath[] = "rei/lastbootcfg"; @@ -69,8 +69,8 @@ void setupCFW(void){ //If L and R are pressed, chainload an external payload if(a9lhBoot && (pressed & BUTTON_L1R1) == BUTTON_L1R1) loadPayload(); - //Check if it's a no-screen-init A9LH boot via PDN_GPU_CNT - if(*(u8 *)0x10141200 != 0x1) loadSplash(); + //Check if it's a no-screen-init A9LH boot + if(PDN_GPU_CNT != 0x1) loadSplash(); /* If L is pressed, and on an updated SysNAND setup the SAFE MODE combo is not pressed, boot 9.0 FIRM */ diff --git a/source/firm.h b/source/firm.h index 38f37c9..614e2b7 100644 --- a/source/firm.h +++ b/source/firm.h @@ -8,8 +8,11 @@ #include "types.h" -#define PDN_MPCORE_CFG (*(u8*)0x10140FFC) -#define HID_PAD ((~*(u16*)0x10146000) & 0xFFF) +#define PDN_MPCORE_CFG (*(vu8 *)0x10140FFC) +#define HID_PAD ((~*(vu16 *)0x10146000) & 0xFFF) +#define PDN_SPI_CNT (*(vu8 *)0x101401C0) +#define CFG_BOOTENV (*(vu8 *)0x10010000) +#define PDN_GPU_CNT (*(vu8 *)0x10141200) #define BUTTON_R1 (1 << 8) #define BUTTON_L1 (1 << 9) #define BUTTON_L1R1 (BUTTON_R1 | BUTTON_L1)