One-liners ftw
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@ -4,6 +4,7 @@
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*/
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#pragma once
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#include "types.h"
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/***
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@ -17,6 +18,5 @@
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void flushEntireDCache(void); //actually: "clean and flush"
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void flushDCacheRange(void *startAddress, u32 size);
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void flushEntireICache(void);
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void flushICacheRange(void *startAddress, u32 size);
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@ -12,11 +12,11 @@
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.global flushEntireDCache
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.type flushEntireDCache, %function
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flushEntireDCache:
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@ Adpated from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0155a/ch03s03s05.html ,
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@ Adapted from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0155a/ch03s03s05.html,
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@ and https://github.com/gemarcano/libctr9_io/blob/master/src/ctr_system_ARM.c#L39 as well
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@ Note: ARM's example is actually for a 8KB DCache (which is what the 3DS has)
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@ Implemented in bootROM at address 0xffff0830
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@ Implemented in bootROM at address 0xffff0830
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mov r1, #0 @ segment counter
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outer_loop:
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mov r0, #0 @ line counter
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@ -39,7 +39,6 @@ flushEntireDCache:
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.type flushDCacheRange, %function
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flushDCacheRange:
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@ Implemented in bootROM at address 0xffff08a0
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add r1, r0, r1 @ end address
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bic r0, #0x1f @ align source address to cache line size (32 bytes)
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@ -57,7 +56,6 @@ flushDCacheRange:
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.type flushEntireICache, %function
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flushEntireICache:
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@ Implemented in bootROM at address 0xffff0ab4
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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bx lr
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@ -66,7 +64,6 @@ flushEntireICache:
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.type flushICacheRange, %function
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flushICacheRange:
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@ Implemented in bootROM at address 0xffff0ac0
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add r1, r0, r1 @ end address
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bic r0, #0x1f @ align source address to cache line size (32 bytes)
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@ -77,4 +74,3 @@ flushICacheRange:
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blo flush_icache_range_loop
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bx lr
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@ -24,7 +24,7 @@ void configureCFW(const char *configPath)
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"( ) SysNAND is updated (A9LH-only)",
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"( ) Force A9LH detection",
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"( ) Use second EmuNAND as default",
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"( ) Enable region/language emu. and external .code loading",
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"( ) Enable region/language emu. and ext. .code",
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"( ) Show current NAND in System Settings",
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"( ) Show GBA boot screen in patched AGB_FIRM",
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"( ) Enable splash screen with no screen-init" };
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