LowLevel/Luma3DS-3GX
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One-liners ftw

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Aurora 2016-07-01 20:36:43 +02:00
parent 136e0d8974
commit 29d8e637d8
3 changed files with 14 additions and 18 deletions
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2
source/cache.h
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@ -4,6 +4,7 @@
*/ */
#pragma once #pragma once
#include "types.h" #include "types.h"
/*** /***
@ -17,6 +18,5 @@
void flushEntireDCache(void); //actually: "clean and flush" void flushEntireDCache(void); //actually: "clean and flush"
void flushDCacheRange(void *startAddress, u32 size); void flushDCacheRange(void *startAddress, u32 size);
void flushEntireICache(void); void flushEntireICache(void);
void flushICacheRange(void *startAddress, u32 size); void flushICacheRange(void *startAddress, u32 size);

8
source/cache.s
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@ -12,11 +12,11 @@
.global flushEntireDCache .global flushEntireDCache
.type flushEntireDCache, %function .type flushEntireDCache, %function
flushEntireDCache: flushEntireDCache:
@ Adpated from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0155a/ch03s03s05.html , @ Adapted from http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0155a/ch03s03s05.html,
@ and https://github.com/gemarcano/libctr9_io/blob/master/src/ctr_system_ARM.c#L39 as well @ and https://github.com/gemarcano/libctr9_io/blob/master/src/ctr_system_ARM.c#L39 as well
@ Note: ARM's example is actually for a 8KB DCache (which is what the 3DS has) @ Note: ARM's example is actually for a 8KB DCache (which is what the 3DS has)
@ Implemented in bootROM at address 0xffff0830
@ Implemented in bootROM at address 0xffff0830
mov r1, #0 @ segment counter mov r1, #0 @ segment counter
outer_loop: outer_loop:
mov r0, #0 @ line counter mov r0, #0 @ line counter
@ -39,7 +39,6 @@ flushEntireDCache:
.type flushDCacheRange, %function .type flushDCacheRange, %function
flushDCacheRange: flushDCacheRange:
@ Implemented in bootROM at address 0xffff08a0 @ Implemented in bootROM at address 0xffff08a0
add r1, r0, r1 @ end address add r1, r0, r1 @ end address
bic r0, #0x1f @ align source address to cache line size (32 bytes) bic r0, #0x1f @ align source address to cache line size (32 bytes)
@ -57,7 +56,6 @@ flushDCacheRange:
.type flushEntireICache, %function .type flushEntireICache, %function
flushEntireICache: flushEntireICache:
@ Implemented in bootROM at address 0xffff0ab4 @ Implemented in bootROM at address 0xffff0ab4
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c5, 0 mcr p15, 0, r0, c7, c5, 0
bx lr bx lr
@ -66,7 +64,6 @@ flushEntireICache:
.type flushICacheRange, %function .type flushICacheRange, %function
flushICacheRange: flushICacheRange:
@ Implemented in bootROM at address 0xffff0ac0 @ Implemented in bootROM at address 0xffff0ac0
add r1, r0, r1 @ end address add r1, r0, r1 @ end address
bic r0, #0x1f @ align source address to cache line size (32 bytes) bic r0, #0x1f @ align source address to cache line size (32 bytes)
@ -77,4 +74,3 @@ flushICacheRange:
blo flush_icache_range_loop blo flush_icache_range_loop
bx lr bx lr

2
source/config.c
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@ -24,7 +24,7 @@ void configureCFW(const char *configPath)
"( ) SysNAND is updated (A9LH-only)", "( ) SysNAND is updated (A9LH-only)",
"( ) Force A9LH detection", "( ) Force A9LH detection",
"( ) Use second EmuNAND as default", "( ) Use second EmuNAND as default",
"( ) Enable region/language emu. and external .code loading", "( ) Enable region/language emu. and ext. .code",
"( ) Show current NAND in System Settings", "( ) Show current NAND in System Settings",
"( ) Show GBA boot screen in patched AGB_FIRM", "( ) Show GBA boot screen in patched AGB_FIRM",
"( ) Enable splash screen with no screen-init" }; "( ) Enable splash screen with no screen-init" };