Fix ldrt/sdrt handling.
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f89845257e
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0ba7630354
@ -67,7 +67,7 @@ void __attribute__((noreturn)) mainHandler(u32 *regs, u32 type, u32 cpuId)
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//Dump registers
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//Current order of saved regs: dfsr, ifsr, far, fpexc, fpinst, fpinst2, cpsr, pc, r8-r12, sp, lr, r0-r7
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u32 cpsr = regs[6];
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u32 pc = regs[7] - (type < 3 ? (((cpsr & 0x20) != 0 && type == 1) ? 2 : 4) : 8);
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u32 pc = regs[7] - (type < 3 ? (((cpsr & 0x20) != 0 && type == 1) ? 2 : 4) : 0);
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registerDump[15] = pc;
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registerDump[16] = cpsr;
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@ -45,7 +45,7 @@ void installArm9Handlers(void)
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}
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}
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u32 installArm11Handlers(u32 *exceptionsPage, u32 stackAddress, u32 codeSetOffset)
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u32 installArm11Handlers(u32 *exceptionsPage, u32 stackAddress, u32 codeSetOffset, u32 *dAbtHandler, u32 dAbtHandlerMemAddress)
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{
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u32 *endPos = exceptionsPage + 0x400;
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@ -67,14 +67,35 @@ u32 installArm11Handlers(u32 *exceptionsPage, u32 stackAddress, u32 codeSetOffse
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exceptionsPage[1] = MAKE_BRANCH(exceptionsPage + 1, (u8 *)freeSpace + *(u32 *)(arm11_exceptions_bin + 8) - 32); //Undefined Instruction
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exceptionsPage[3] = MAKE_BRANCH(exceptionsPage + 3, (u8 *)freeSpace + *(u32 *)(arm11_exceptions_bin + 12) - 32); //Prefetch Abort
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exceptionsPage[4] = MAKE_BRANCH(exceptionsPage + 4, (u8 *)freeSpace + *(u32 *)(arm11_exceptions_bin + 16) - 32); //Data Abort
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exceptionsPage[7] = MAKE_BRANCH(exceptionsPage + 7, (u8 *)freeSpace + *(u32 *)(arm11_exceptions_bin + 4) - 32); //FIQ
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for(u32 *pos = dAbtHandler; *pos != stackAddress; pos++)
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{
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u32 va_dst = 0xFFFF0000 + (((u8 *)freeSpace + *(u32 *)(arm11_exceptions_bin + 4)) - (u8 *)exceptionsPage);
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u32 va_src;
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switch(*pos)
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{
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case 0xF96D0513: //srsdb sp!, 0x13
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va_src = dAbtHandlerMemAddress + ((u8 *)pos - (u8 *)dAbtHandler);
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*pos = MAKE_BRANCH((u8 *)va_src, (u8 *)va_dst);
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break;
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case 0xE29EF004: //subs pc, lr, 4
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pos++;
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*pos++ = 0xE8BD000F;// pop {r0-r3}
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va_src = dAbtHandlerMemAddress + ((u8 *)pos - (u8 *)dAbtHandler);
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*pos = MAKE_BRANCH((u8 *)va_src, (u8 *)va_dst);
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break;
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default:
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break;
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}
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}
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for(u32 *pos = freeSpace; pos < (u32 *)((u8 *)freeSpace + arm11_exceptions_bin_size - 32); pos++)
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{
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switch(*pos) //Perform relocations
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{
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case 0xFFFF3000: *pos = stackAddress; break;
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case 0xFFFF3000: *pos = stackAddress - 0x10; break;
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case 0xEBFFFFFE: *pos = MAKE_BRANCH_LINK(pos, initFPU); break;
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case 0xEAFFFFFE: *pos = MAKE_BRANCH(pos, mcuReboot); break;
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case 0xE12FFF1C: pos[1] = 0xFFFF0000 + 4 * (u32)(freeSpace - exceptionsPage) + pos[1] - 32; break; //bx r12 (mainHandler)
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@ -28,5 +28,5 @@
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#define MAKE_BRANCH_LINK(src,dst) (0xEB000000 | ((u32)((((u8 *)(dst) - (u8 *)(src)) >> 2) - 2) & 0xFFFFFF))
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void installArm9Handlers(void);
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u32 installArm11Handlers(u32 *exceptionsPage, u32 stackAddress, u32 codeSetOffset);
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u32 installArm11Handlers(u32 *exceptionsPage, u32 stackAddress, u32 codeSetOffset, u32 *dAbtHandler, u32 dAbtHandlerMemAddress);
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void detectAndProcessExceptionDumps(void);
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@ -136,8 +136,9 @@ u32 patchNativeFirm(u32 firmVersion, FirmwareSource nandType, u32 emuHeader, boo
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u32 baseK11VA;
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u8 *freeK11Space;
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u32 *arm11SvcHandler,
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*arm11DAbtHandler,
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*arm11ExceptionsPage,
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*arm11SvcTable = getKernel11Info(arm11Section1, firm->section[1].size, &baseK11VA, &freeK11Space, &arm11SvcHandler, &arm11ExceptionsPage);
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*arm11SvcTable = getKernel11Info(arm11Section1, firm->section[1].size, &baseK11VA, &freeK11Space, &arm11SvcHandler, &arm11DAbtHandler, &arm11ExceptionsPage);
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u32 kernel9Size = (u32)(process9Offset - arm9Section) - sizeof(Cxi) - 0x200,
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ret = 0;
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@ -185,7 +186,7 @@ u32 patchNativeFirm(u32 firmVersion, FirmwareSource nandType, u32 emuHeader, boo
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//ARM11 exception handlers
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u32 codeSetOffset,
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stackAddress = getInfoForArm11ExceptionHandlers(arm11Section1, firm->section[1].size, &codeSetOffset);
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ret += installArm11Handlers(arm11ExceptionsPage, stackAddress, codeSetOffset);
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ret += installArm11Handlers(arm11ExceptionsPage, stackAddress, codeSetOffset, arm11DAbtHandler, baseK11VA + ((u8 *)arm11DAbtHandler - arm11Section1));
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patchSvcBreak11(arm11Section1, arm11SvcTable);
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ret += patchKernel11Panic(arm11Section1, firm->section[1].size);
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@ -73,7 +73,7 @@ u8 *getProcess9Info(u8 *pos, u32 size, u32 *process9Size, u32 *process9MemAddr)
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return (u8 *)off + (off->ncch.exeFsOffset + 1) * 0x200;
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}
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u32 *getKernel11Info(u8 *pos, u32 size, u32 *baseK11VA, u8 **freeK11Space, u32 **arm11SvcHandler, u32 **arm11ExceptionsPage)
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u32 *getKernel11Info(u8 *pos, u32 size, u32 *baseK11VA, u8 **freeK11Space, u32 **arm11SvcHandler, u32 **arm11DAbtHandler, u32 **arm11ExceptionsPage)
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{
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const u8 pattern[] = {0x00, 0xB0, 0x9C, 0xE5},
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pattern2[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
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@ -87,11 +87,14 @@ u32 *getKernel11Info(u8 *pos, u32 size, u32 *baseK11VA, u8 **freeK11Space, u32 *
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*arm11ExceptionsPage -= 0xB;
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u32 svcOffset = (-(((*arm11ExceptionsPage)[2] & 0xFFFFFF) << 2) & (0xFFFFFF << 2)) - 8; //Branch offset + 8 for prefetch
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u32 dabtOffset = (-(((*arm11ExceptionsPage)[4] & 0xFFFFFF) << 2) & (0xFFFFFF << 2)) - 8; //Branch offset + 8 for prefetch
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u32 pointedInstructionVA = 0xFFFF0008 - svcOffset;
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*baseK11VA = pointedInstructionVA & 0xFFFF0000; //This assumes that the pointed instruction has an offset < 0x10000, iirc that's always the case
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arm11SvcTable = *arm11SvcHandler = (u32 *)(pos + *(u32 *)(pos + pointedInstructionVA - *baseK11VA + 8) - *baseK11VA); //SVC handler address
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while(*arm11SvcTable) arm11SvcTable++; //Look for SVC0 (NULL)
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pointedInstructionVA = 0xFFFF0010 - dabtOffset;
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*arm11DAbtHandler = (u32 *)(pos + *(u32 *)(pos + pointedInstructionVA - *baseK11VA + 8) - *baseK11VA);
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(*freeK11Space)++;
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return arm11SvcTable;
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@ -35,7 +35,7 @@
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extern CfgData configData;
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u8 *getProcess9Info(u8 *pos, u32 size, u32 *process9Size, u32 *process9MemAddr);
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u32 *getKernel11Info(u8 *pos, u32 size, u32 *baseK11VA, u8 **freeK11Space, u32 **arm11SvcHandler, u32 **arm11ExceptionsPage);
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u32 *getKernel11Info(u8 *pos, u32 size, u32 *baseK11VA, u8 **freeK11Space, u32 **arm11SvcHandler, u32 **arm11DAbtHandler, u32 **arm11ExceptionsPage);
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u32 patchSignatureChecks(u8 *pos, u32 size);
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u32 patchFirmlaunches(u8 *pos, u32 size, u32 process9MemAddr);
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u32 patchFirmWrites(u8 *pos, u32 size);
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