Add proper arm11 crt0 and fix race condition

arm11/linker.ld

@@ -8,7 +8,8 @@ SECTIONS
 
     .text   : ALIGN(4) { *(.text.start) *(.text*); . = ALIGN(4); }
     .rodata : ALIGN(4) { *(.rodata*); . = ALIGN(4); }
-    .data   : ALIGN(4) { *(.data*); . = ALIGN(8); *(.bss* COMMON); . = ALIGN(8); }
+    .data   : ALIGN(4) { *(.data*); . = ALIGN(4); }
+    .bss    : ALIGN(8) { __bss_start = .; *(.bss* COMMON); . = ALIGN(8); __bss_end = .; }
 
     __stack_top__    = 0x1FFFF000;
     . = ALIGN(4);

arm11/source/main.c

@@ -194,9 +194,7 @@ void main(void)
             case PREPARE_ARM11_FOR_FIRMLAUNCH:
                 memcpy((void *)0x1FFFFC00, (void *)prepareForFirmlaunch, prepareForFirmlaunchSize);
                 *(vu32 *)0x1FFFFFFC = 0;
-                operation = ARM11_READY;
+                ((void (*)(u32, volatile Arm11Operation *))0x1FFFFC00)(ARM11_READY, &operation);
-                ((void (*)(void))0x1FFFFC00)();
-                break;
         }
 
         operation = ARM11_READY;

arm11/source/memory.c

@@ -33,4 +33,20 @@ void memcpy(void *dest, const void *src, u32 size)
 
     for(u32 i = 0; i < size; i++)
         destc[i] = srcc[i];
-}
+}
+
+void memset(void *dest, u32 filler, u32 size)
+{
+    u8 *destc = (u8 *)dest;
+
+    for(u32 i = 0; i < size; i++)
+        destc[i] = (u8)filler;
+}
+
+void memset32(void *dest, u32 filler, u32 size)
+{
+    u32 *dest32 = (u32 *)dest;
+
+    for(u32 i = 0; i < size / 4; i++)
+        dest32[i] = filler;
+}

arm11/source/memory.h

@@ -28,4 +28,6 @@
 
 #include "types.h"
 
-void memcpy(void *dest, const void *src, u32 size);
+void memcpy(void *dest, const void *src, u32 size);
+void memset(void *dest, u32 value, u32 size) __attribute__((used));
+void memset32(void *dest, u32 filler, u32 size);

arm11/source/start.s

@@ -31,12 +31,38 @@ operation:
 
 start:
     cpsid aif
+
+    @ Set the control register to reset default: everything disabled
+    ldr r0, =0x54078
+    mcr p15, 0, r0, c1, c0, 0
+
+    @ Set the auxiliary control register to reset default.
+    @ Enables instruction folding, static branch prediction,
+    @ dynamic branch prediction, and return stack.
+    mov r0, #0xF
+    mcr p15, 0, r0, c1, c0, 1
+
+    @ Invalidate all caches, flush the prefetch buffer and DSB
+    mov r0, #0
+    mcr p15, 0, r0, c7, c5, 4
+    mcr p15, 0, r0, c7, c5, 0
+    mcr p15, 0, r0, c7, c6, 0
+    mcr p15, 0, r0, c7, c10, 4
+
+    @ Clear BSS
+    ldr r0, =__bss_start
+    mov r1, #0
+    ldr r2, =__bss_end
+    sub r2, r0
+    bl memset32
+
     ldr sp, =__stack_top__
     b main
 
 .global prepareForFirmlaunch
 .type   prepareForFirmlaunch, %function
 prepareForFirmlaunch:
+    str r0, [r1]            @ tell ARM9 we're done
     mov r0, #0x20000000
 
     _wait_for_core0_entrypoint_loop: