58 lines
1.5 KiB
ArmAsm
58 lines
1.5 KiB
ArmAsm
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@ handlers.s
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@ by TuxSH
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@
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@ This is part of Luma3DS, see LICENSE.txt for details
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@
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.macro GEN_HANDLER name, addr_offset
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.global \name
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.type \name, %function
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\name:
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stmfd sp!, {r0-r7} @ FIQ has its own r8-r14 regs
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ldr r0, =\addr_offset
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sub r0, lr, r0 @ address of instruction that triggered the exception; we will handle the undef+Thumb case later
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mrs r2, spsr
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mov r6, sp
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mrs r3, cpsr
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ands r4, r2, #0xf @ get the mode that triggered the exception
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moveq r4, #0xf @ usr => sys
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bic r5, r3, #0xf
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orr r5, r4
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msr cpsr_c, r5 @ change processor mode
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stmfd r6!, {r8-r14}
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msr cpsr_c, r3 @ restore processor mode
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mov sp, r6
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stmfd sp!, {r0,r2} @ it's a bit of a mess, but we will fix that later
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@ order of regs now: pc, spsr, r8-r14, r0-r7
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mov r0, sp
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ldr r1, =\@ @ macro expansion counter
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b mainHandler
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.size \name, . - \name
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.endm
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.text
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.arm
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.align 4
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GEN_HANDLER FIQHandler, 4
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GEN_HANDLER undefinedInstructionHandler, 4
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GEN_HANDLER prefetchAbortHandler, 4
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GEN_HANDLER dataAbortHandler, 8
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.global setupStack
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.type setupStack, %function
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setupStack:
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cmp r0, #0
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moveq r0, #0xf @ usr => sys
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mrs r2, cpsr
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bic r3, r2, #0xf
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orr r3, r0 @ processor mode
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msr cpsr_c, r3 @ change processor mode
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mov sp, r1
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msr cpsr_c, r2 @ restore processor mode
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bx lr
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